Application Research And Optimum Design Of 8051 MCU IP Core

Based on IP reusable technology and Hardware description language, this thesis uses the advanced digital design methods to implement a 8 bit microprocessor which is fully compatible with MCS-8051 MCU family. The IP core is successfully synthesized and downloaded into FPGA chip and make physical verifications.Before apply the IP core in 8 bit MCU ES, there are some works having been done to ensure the system work stably, such as verifying and simulation. Based on thorough analysis of Intel MCU-8051 functions and technology, this paper completely describes how to make function simulation with each module and how to verify the instruction sets using QuartusII5.0 Platform.By analyzing the results of synthesis and function simulation, a optimum IP core design is brought forward. The advanced IP core consume less chip area and execute at a higher speed. To achieve less area some instructions which are seldom used have not been synthesized, such as MUL, DIV, DA. The memory space also have been modified according to the target FPGA chip, some address bus and memory interface have been redefined. To run at a higher speed, the program flow concept is introduced and applied. This refer to arithmetic and logic instructions, data transfer instructions and bit addressable instructions. To prove the possibility the IP core is verified with ModelsimSE simulator.Finally, the IP core is download into FPGA chip(EP2C8Q208C8) to make physical tests. Two experiments are done. One is the led shinning experiment, the other is step motor driving experiment. By contrast the control effects and test wave of the advanced IP and original IP, the new IP achieves the expect goals.Through s imulation and e xperiments we make conclusions that the optimum 8051 IP core can be applied in traditional 8051 MCU system fully compatibly and stably. The design has its useful value in research on ES and SoC based on 8 bit MCU.