Hardware Design Based On FPGA For Compressive Sensing In Body Area Network

The coming of information society increase the amount of information to beprocessed greatly. The traditional Nyquist sampling theorem states that the samplingrate must be twice more than the signal bandwidth in order to reconstruct the signalaccurately. Such way of sampling transform the input analog signal into digital signalby with a high speed and then compress the data, which increase the storage,processing, transmission costs of information, resulting in a waste of resources. Anew theory-compressed sensing emerged in recent years.Compressed sensing theorybreaks through the traditional Nyquist sampling. It points out that, as long as thesignal is a compressible or sparse in transform domain, then we can use ameasurement matrix to project a high-dimensional signal onto a lower dimensionalspace,which is not correlated with transform basis and then reconstruct the originalsignal form a few of measurement with high probability by solving a optimizationproblem. Compressive sensing carry out capture and compression simultaneously,sample at a lower rate, thus effectively reduce the amount of data and the powerconsumption of the device, which is meaningful for applications that has low powerrequirement, such as wireless body area network.In the paper, I apply compressedsensing theory in the acquisition and processing of ECG signal in wireless body areanetwork, expecting reduce power consumption by reducing the amount of collecteddata.This paper first introduces the basic concepts and principles of compressedsensing. Take one-dimensional and picture signal for example, do some performancesimulation of compressed sensing theory algorithm. Since the ECG data to becollected is an analog signal, it is significant that the compressed sensing theoryapplied to the analog domain, so I study Anolog Information Converter, namely AICsystem structure. Finally, apply the AIC system model in ECG acquisition, andpropose AIC ECG acquisition system design based on FPGA.