Implementation Of The FPGA And Signal Reconstruction Algorithm Research Based On Compressed Sensing

In recent years, compressed sensing is the rise of a novel sampling theory, the theory provides a method that it can precise reconstruct of the original signal from a small amount of sampling value. Since the theory was presented, it has gained attention due to its promising practical potentials. Improving the quality of signal reconstruction and designing a reconstruction algorithm with low complexity, it is one of the focal points and hot problems of studying in the related field. Given this, the article has deeply studied the compressed sensing reconstruction algorithms for signal in order to find robust and effective reconstruction algorithms. The main contribution and innovations of the dissertation are as follows.First of all, our research build in compressed sensing image reconstruction algorithm based on pl norm reconstruction, in view of Lagrange function series Quadratic Programming(SQP) method to the Hesse is not positive definite matrix calculation in a lot of problems, this paper proposes a image reconstruction algorithm based on pl norm compression awareness. The algorithm introduces the value function, correcting matrix sequence Quadratic Programming method and combined with the image block compressed sensing technology, in the different sampling rates and different reconstruction algorithms, by comparing the results of image reconstruction. The experimental results show that the proposed algorithm can achieve a balance between reconstruction accuracy and time.Secondly, in view of the problem of compression sensing reconstruction algorithm of Orthogonal Matching Pursuit(OMP) algorithm in each iteration can’t select the optimal atomic, improved atom selection criteria, it ensures that each iteration of the current allowance minimum observation signal, and proposes a kind of optimize the OMP algorithm to realize the hardware structure design based on FPGA. In the matrix decomposition part adopts corrected Cholesky column decomposition method, avoid root operation, to reduce the calculation time delay, and it can easy to FPGA implementation.And lastly, the image acquisition and processing hardware system has been designed based on FPGA in the article. The design has realized the compression of image acquisition perception. It gives the details of the modular design, it mainly including CMOS camera and chip CY7C68013 initialization configuration, I2 C configuration module, duplex SDRAM read and write control module, image processing module. Through the USB2.0 interface communication complete image data transmission, and by means of the VS2010 design of USB2.0 high speed interface communication of upper machine software.