Research And Implementation Of Compressed Sensing Recovery Algorithm Based On FPGA

Nowadays, in this digital information age, the explosing information gives an enormous challenge on the signal acquisition, transmission, storage and processing. Compressed sensing is a new sampling theory developed in recent years. With this method, we can capture and represent the compressible signal at a sampling rate significantly below the Nyquist rate by exploring the compressibility of the signal. Then the signal reconstruction is conducted by recovery algorithms. This theory is an effective way to ease the pressure to achieve high-speed sampling and to decrease the data transmission and storage costs, which has attracted great attention in various applications. Currently, compressed sensing signal recovery algorithms are mostly implemented with computer software. Due to large computational intensity of the algorithms and performance limitations of the computer itself, software implementation of these algorithms is slow, which limits the application of compressed sensing. Meanwhile, with the advantages of high parallelism, fast computing speed, high efficiency and easy cutting features, the ASIC and FPGA are very suitable for complex algorithms to increase the speed. In this paper, a compressed sensing reconstruction hardware architecture based on FPGA was proposed to meet the needs of real-time applications.The compressed sensing theory is used for the single photon counting imaging system in this paper, which can solve the problems of the restricted unit-pixel sensitivity of the focal plane array detector and mounts of measurements requirements. However, it costs huge computing consumption and long recovery time at the data recovery end. Therefore, it is urgent to increase the imaging speed. However, replacing software implementation with hardware implementation of the compressed sensing recovery algorithm can accelerate the recovery of the imaging system.Specifically, the proposed hardware architecture based on the orthogonal matching pursuit(OMP) algorithm can be divided into two parts: to find the best matches atom and to solve the least squares problem. Firstly, parallel multiply accumulators are used to find the best match atoms among the measurement matrix. Secondly, the least squares problem is solved with QR decomposition, which is implemented based on the coordinate rotation digital computation(CORDIC) method. The hardware architecture improves the systolic array module and the corresponding scheduling processing module by adding delay units and then gets the results. The hardware can reconstruct an 8-sparse signal of column dimension 256 and on this basis a 256 × 256 image can be reconstructed in the order of columns.Experimental results show that the proposed hardware architecture for 256-length vector of sparsity 8 takes 0.296 ms, which is nearly 18 times faster than the software on the PC. It takes 69.703 ms to reconstruct a 256 × 256 image which is nearly 12 times faster than the software on the PC. And the PSNR drops only 0.001 d B which shows the quality of the reconstructed image is essentially the same. Furthermore, the mean square error(MSE) values of the signals reconstructd by the software and hardware are almost the same. Finally, experiments show that the hardware applied to the single photon counting imaging system not only improves the speed but also reaches the same recovery effect compared with the software on PC.