The Optimization Technology And Chip Test Of High-performance Digital Signal Processor Core

YHFT-DX DSP Core is designed with65nm CMOS process to achieve800MHz under theworst conditions. It is the key to meet the DSP requirements. In the background of DataPath andlevel-one cache performance optimization, this paper has researched the RTL-level codeoptimization technologies, circuit design and optimization technologies, and semi-custom designmethodology. The main works in the paper are:1．The function cells and level-one cache of the DSP Core have been full optimized inRTL-level, the memory access unit and multiplier unit are the key points of optimization. Theeffective methods of optimization have many sides, like reduce multiplex ports, logic transplant,logic copy, algorithm parallel. After optimization, the synthesis of CPU Core has no slack in1ns clock period.2． The adder and multiplier of the DSP Core are realized by semi-custom designmethodology. For optimizing the memory access unit performance, a32-bit adder is designed bysemi-custom design method based on standard cell. By simulation results, the sum of32-bitadder is equal to full-custom design, but the period is decreased50%. We use another way todesign16-bit SIMD multiplier, which is using full-custom design method to realize key path,and the other parts is designed with standard automatic place a nd route. Simulation results showthat the delay of this multiplier is decreased24%. If these methods are used in the right way, itcan enhance the design performance, reduce the design cycle and cost.3．In order to verify the efficiency of YHFT-DX DSP Core optimization, we need to have aMPW die. Therefore, a DSP Core testchip is designed. It can load programme and data to theCPU and export the execution results. The testchip has been tested after fabricated. The testresults show that YHFT-DX DSP Core can work normally in frequence up to900MHz when thevoltage is1v. All of the results indicate that all the optimization technologies are available.