Research On Topology Of NoC For Three Dimensional Multi-core Microprocessors

In the era of Multi-core, microprocessor designing is facing some worseningproblems such as power consumption, memory access and interconnection. Threedimensional integrated circuit (3D IC) is a new integrated circuit technology. Byconnecting multilayer silicon wafer via through silicon via (TSV), it can improve theresources of the single chip package, shorten the global connections, thus making thechip internal able to accommodate more cores and related resources. Networks-on-Chip(NoC) is a structured interconnection design method to face with the needs ofmulti-core and many-core processor communication.3D IC and NoC are both importantdeveloping directions of large scale integrated circuit design. Three dimensionalnetworks on chip (3D NoC), which combines the advantage of3D IC and NoC, hasmore interconnect components, high bandwidth and low latency.3D NoC is one of thehot spots of current research.Although the possibility of stacking10layer above dies has been proved, currentstudy of three dimensional networks-on-chip topology are all for the less layer aroundfour, which goes no further. By utilizing TSV’s characteristics of short delays and lesspower consumption, this paper has designed a new kind of topology3DE-Mesh for a3D NoC that has more than10layers of stacked dies. By analyzing the experimentaldata, this paper proves that3DE-Mesh is suitable for the three dimensional integratedcircuits that has more than10layers of stacked dies, on the aspects of function andscalability.Existing3D NoC researches mainly use fixed structure routers, the networkfunctioning performance of which decreases as the stacked layers accumulates; on theother hand, they have not made use of the characteristics of through silicon via (TSV) in3D IC, which include short delaying and low power consumption. For the purposes offully exploring the TSV characteristics and facing the extending need of multiplestacking TSV layers in the future, this paper has designed a kind of express inter diesrouter (EIDR). On using the single hop inter dies (SHID) architecture established by thiskind of router, TSV amount increases, thus improves the performance. Analysis on theexperimental data show that compare with the two existing3D NoC structures of3D-Mesh and NoC-Bus, SHID architecture has some characteristics:1) The latency ofSHID architecture is lower. It is15.1%lower than3D-Mesh and11.5%lower thanNoC-Bus when stacking4layers;2) The power consumption of SHID architectureequals NoC-Bus and is10%lower than3D-Mesh;3) Throughput of SHID architecturedecrease slower as the number of stacked layers increases. It is66.98%higher than3D-Mesh and314.49%higher than Noc-Bus when stacking16layers.Multi-layer stacked3D topology3DE-Mesh and SHID make up the disadvantage of insufficient expansion of the existing three dimensional NOC structure study, and hasadvantage in the performance and scalability. It is a well design choice for future3DNoC architecture.