Design And Implementation Of On Chip AXI Bus Bridge Controller For High-performance X-QDSP Based On DMA Mechanism

As DSP technologies are continuously developing, digital signal processing isgrowing improved. The realization of high-speed data transmission with complicatedcontrols of multiple bus structure is becoming one of the most key parts of designationfor modern DSP. The X-QDSP, whose Switch Bus contains8sets of read and writebuses in internal bus control center and has a totally different structure with AXI, is ahigh-performance chip with complicated bus system. A128bits AXI bus bridgecontroller is proposed to deal with the high-speed interconnect between SRIO IP corewith AXI interface and system bus, which realizes the perfect connection between AXIand various bus protocols on chip.Transmission protocols were deeply analyzed in terms of complexity of themultiple bus controllers. A bus arbitrator through incorporating fixed priority with tokenrotation is provided to avoid the congestion of data transmission.An AXI bus bridge controller that contains four independent and concurrent readand write channels is proposed to achieve diversity data transmission. It includes twoSRIO master channels, which are with DMA function to accomplish backgroundoperation, to deal with the data transmission started by DSP core, and two SRIO slavechannels to validate the well-off of data transmission when receiving a request fromSRIO which will be transformed into transfer instruction on the Switch Bus.Each channel with different depth of buffer is adopted to tackle transmission issuesabout data merging, splitting control and misaligned addresses based on itscharacteristic. The bridge-interconnections among different transmission manners orbus protocols with different bit width are achieved by utilizing central control ofstate-machine, which ensure the high-speed data transmission. Additionally, anasynchronous FIFO scheme is proposed to realize the asynchronous FIFO with4depthand asynchronous connections between SRIO and on-chip system bus.Module-level, component-level and system-level functional verifications andstatistical code coverage rate have been performed to verify satisfactions for allrequirements of the chip.All simulations are logical synthesized exploiting65nm process, and the structureand timing optimization are also performed. The experimental results show that the AXIbus bridge controller is a500MHZ achievable frequency in the worst case.