The Research And Implemention For OCV Analysis Method Based On Path

As integrated circuit technology turns into the nanometer process, on-chipvariation (OCV) becomes more and more serious. In order to cover all design situations,the current design method adopts the relatively pessimistic settings which set the OCVfactors as the foundries recommend. The variation is far below the recommended valuewhen the IR_drop is at a low level. In addition, Static timing analysis (STA) method isbased on the worst case of device analysis, while the actual variation of each part ofpath is not skewed in the same direction. In the case of depth path, the internal balancemakes the overall delay variation much less than the worst case. Therefore, the issue ofOCV pessimism will greatly lead to the difficulty of timing signoff and extra costs.The main work and specific activities are as follows:1) Research the mechanism of OCV by comparing the difference between globalvariation and local variation which affects the timing.2) In order to adjust the range of local variation according to different designspecific, we use the local variation statistical model of SPICE to simulate the OCV andalso take the local voltage variation into consideration on the basis of the originalmodel.3) Based on the above research, we use the path based OCV analysis method toreduce the OCV pessimism. This method analyzes the path as a whole; considers theOCV balance among the internal devices and statistical distribution of path delay whichuses Monte Carlo mode stimulated based on±3σstandard deviation. This methodconfirms that deeper the path stage is, the less OCV are; OCV also becomes smallerwhen the IR-drop is at a lower degree.4) Based on the above methods, A new static timing analysis flow is proposed byusing Primetime、SPICE tool and TCL script. This flow is used to solve the problem ofOCV pessimism under the situation of depth path and low IR-drop in timing closure.The flow which is applied to the above design situations and experimented on threedesign instances achieves3%~5%timing improvements respectively compared with theoriginal OCV method, and reduces the number of violation paths and design cost. Theabove results confirm the effectiveness of this flow. What’s more, this method is similarwith the AOCV method which is provided by commercial tools, so it can be applied toVLSI design and the complexity of design will be reduced, as well as cost.