Research And Design Of A High-Speed Large-Capacity Radar Storage System

Airborne SAR is typically a complex system with high storage capacity and high processing ability. Therefore, as a fundamental device of radar imaging system, the storage subsystem should be able to satisfy the strict requirements on storage capacity and data transfer speed. In this thesis, we put forward a design of a high storage capability and real time solid state storage system, providing 2TByte storage capability and 1GByte/s data transfer speed. This is a leading radar storage solution in domestic market, which can provide high speed, large capacity and high reliability.In this thesis, we analyze and describe the system structure, storage mechanism, error correcting mechanism and data transfer of this storage system. We also design the FPGA control logic and hardware circuits.Firstly, after analyzing current storage media’s features and the features of SAR imaging system, NAND FLASH is used in this design. A parallel and pipeline storage mechanism is introduced in order to increase the writing and reading speed as well as providing high storage capability. An error correcting mechanism is utilized, using FPGA’s Block SelectRAM+, in case new invalid blocks appear when programming or erasing NAND FLASH. A file system is also design to support multi-files storage as well as ensure the system’s reliability.After analyzing the current high speed data interface, RocketIO and Aurora protocol are used in this system, providing 1GByte/s data transfer speed and high data reliability. Physical and data-link layer is implemented. Besides, in order to align the data among multi RocketIO interfaces, a frame alignment method is put forward.The FPGA logic design in this system provides control and management of data communication, FLASH operation and file system. Several key points in hardware schematics design are also described. At last, writing and reading speed is theoretically analyzed and compared to practical application.