The Process Integration Design For SiGe HBT

Demands are improving rapidly for RF semiconductor devices with higher performance and lower cost, due to the development of modern mobile communications. Traditional Si devices are unable to meet the new requirements of higher performance in high frequency and lower cost. So the SiGe/Si devices have been proposed and investigated ,whose fabrication process is compatible with traditional Si process so as to reduce fabrication costs. According to the characteristics of SiGe HBT, such as holding high performance as GaAs which can meet the demand with RF ICs and having low cost because of the compatibility with Si technology,SiGe HBT has become one of the hot fields in the world.Cooperating with the J FAB that has the international mature SiGe BiCMOS technology, a practicable 0.35μm SiGe BiCMOS flow is developed. SiGe BiCMOS device structures are also designed. The process is based on deep trench isolation, non-selective epitaxy, with collector selective implantation and in-situ arsenic doped emitter poly deposition. This design greatly enhances the device performance and makes the process more feasible. The compatibility with Si CMOS device structure has been considered thoroughly in design. The process of CMOS gate, ploy Si gate, and SiGe HBT ex-base have been optimized in order to simplify the flow. As a result, the integrated level has been improved.The emphasis of this thesis is the process integration design that how to improve the performance of SiGe HBT transistor .Through theoretical analysis and result of experiment SiGe HBT optimization rules and design steps for 0.35μm SiGe BiCMOS are presented, which include:(1) A Process Integration Method to improve SiGe HBT Beta linearity;(2) A Process Integration Method to reduce the oxide micro defect pre SIGE depositon. According to these optimization rules, a SiGe HBT for BiCMOS technology has been designed. The experiment results show that the performance of the SIGE HBT have been obviously improved by the process integration optimization disign...