Research And Design Of Optical Receiver With Common-Emitter And Common-Gate Stacked Amplifier Based On Standard SiGe BiCMOS Process

With the increasement of data volume used in communication, the traditionalcommunication network cannot meet the need of exchanging information, which leadsto the development of networks of fiber communication. Optic-fiber communicationsystems are the principal parts of information super-highway for its merits such asgreat capacity, long transmit distance, economizing energy source, anti interferenceand anti radiation etc. Optical receiver is one of the core devices of Optic-fibercommunication systems, therefore, more and more scientists engaged in thedevelopment of low-cost high-performance optical receiver. Compared to thehybrid-integrated photo-receiver and the monolithic CMOS optoelectronic integratedreceiver，the monolithic SiGe BiCMOS optoelectronic integrated receiver not onlyreduces the cost of receiver greatly，but also improves bandwidth and sensitivity ofthe optical receiver. So, many domestic and foreign scholars undertaken extensiveresearch and report in recent years.This paper presents a monolithically integrated optical receiver realized withIBM7WL SiGe BiCMOS process. The optical receiver includes two heterojunctionPIN photodetector, two common-emitter and common-gate （CE and CG）transimpedance amplifiers (TIA), four limiting amplifiers and an output buffer.In this paper, a heterojunction PIN photodetector is designed and fabricated inSiGe BiCMOS process. The photodetector achieves0.26A/W responsivity and7.9GHz bandwidth for an850nm input optical signal.The common-emitter and common-gate TIA with SiGe heterojunction bipolartransistor (HBT) input stage reduce the input resistance, and isolate the effects of theparasitic photodetector capacitance, thus expand effectively the bandwidth of theoptical receiver. The simulated results indicate that the optical receiver terminatedwith50Ω load resistance and10pF load capacitance has a transimpedance gain of76.67dB, and a-3dB bandwidth of2.1GHz. The experimental results indicate that adata rate of1.5Gb/s is successfully realized at a bit-error rate of10-9, and the receiverachieves a72.2dB transimpedance gain with a1.2GHz bandwidth. Total chip powerincluding the output buffer is44mW from1.8V supply, and the chip area includingpads is800μm×370μm.