Algorithms Design And Implementation Of H.264/AVC Motion Estimator

H.264/AVC is a new video coding international standard proposed by Joint Video Team (JVT), which organized by the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG). H.264/AVC has many advantages such as high compressing gain, strong error recovery ability, wide application fields. In order to achieve high compressing gain, some new complicated algorithms are introduced in H.264/AVC, which bring higher computation complexity.H.264/AVC motion estimator used in handheld devices must satisfy the requirements in cost and area. Firstly, computation complexity needs to be reduced in order to lower the frequency of motion estimator. Secondly, the size of handheld devices is small, so we should try our best to reduce hardware resource consumption in certain frequency.Based on the two points above and characteristics of small size video, we propose an optimized algorithm and VLSI architecture design of H.264/AVC motion estimator. Our job includes as follows:1.Algorithm design. According to requirements, we choose a proper pixel ME algorithm, and design optimized variable block size ME algorithm, multi-frame ME algorithm and sub-pixel ME algorithm. Optimized algorithms reduce computation complexity to a great extent while PSNR and bitrate don’t change much. And the integrated ME algorithms are fit for VLSI implementation.2.Flow optimization. After analyzing zero-detection algorithm, we change the position of SKIP mode computation in ME algorithm flow and design a criterion to determine whether to compute SKIP mode. Optimized flow shows the advantage of SKIP mode and meanwhile avoids the effect it brings to other modes.3.Architecture design. The system architecture is devided into three major portions: PE array, Quarter-Pixel Interpolation Engine and on-chip memory access strategy.Based on intra-level architecture, PE array utilizes 4-row processing element (PE) to implement the block-matching search. Considering both proper work frequency and hardware cost, We adopt several 6-tap filters and 2-tap filters to generate 1/2 and 1/4 luma pixels and 2-stage pipeline to generate 1/8 chroma pixels. We design a reasonable on-chip memory allocation strategy. By expanding reference data local memory, the data path is simplified.All in all, our optimized algorithms reduce computation complexity to a great extent while PSNR and bitrate don’t change much. Optimized flow shows the advantage of SKIP mode and accelerates the ME computation. According to the tradeoff between performance and frequency, the architecture not only satisfies the performance requirements but also consumes less hardware resources.