Research And Design On Full Search Block Matching Motion Estimation Architecture

As a vital part of video coding system, motion estimation (ME) can remove most of temporal redundancy, spatial redundancy from video signal. Thus a high compression ratio of video data can be achieved, further facilitating storage and transmission of massive digital video information.Motion estimation, though may be easily conceptualized as the computing process of motion vector (MV), has a lot worth studying in terms of the research and practice on the algorithm and architecture level.More importantly, with actually no restriction imposed on the implementation part by any video coding standard, motion estimation circuit has a large design space to explore. Among which, a class of motion estimation architecture, based on Full Search Blocking Matching (FSBM) ME algorithm, has received most attention from the academia, because of the best picture quality under compression, and its very hardware-design friendly feature of high data access regularity.However this class of ME architecture has huge data volume to be process and naturally is subject to great power dissipation. For this very reason, study on this class of architecture becomes the topic of this research work.The thesis carefully studies the design space of this ME architecture class, and presnets a new structurally-optimized,high-performance low-bandwidth ME architecture, toward full search variable block sized motion estimation (VBSME), targeting the new mainstream video coding standard, H.264/AVC.