| There is an increasing need for high quality video on low power, low bit rate, portable devices. The possible applications on these devices range from entertainment and personal communications to security and health care. While H.264/AVC, the most recent video coding standard, answers the need for high quality video at lower bit rates than were previously the case, it is significantly more complex than previous coding standards and thus results in greater power consumption in practical implementations. In particular, motion estimation, the most effective compression tool in H.264/AVC, consumes up to 80% of the total encoding time. This means that ME consumes the largest power in an H.264/AVC encoder. It is therefore critical to speed up motion estimation in H.264/AVC in order to meet real-time and low power requirements.;Two approaches to motion estimation speed-up in H.264/AVC are designing fast motion estimation algorithms and employing hardware acceleration. In this dissertation, we propose solutions that combine both of these approaches. Our main contributions in this dissertation are as follows:;We propose hardware oriented modifications to the hybrid fast motion estimation algorithm --- Simplified Unified Multi Hexagon (SUMH). The resulting algorithm is called Modified SUMH. We propose supporting hardware architecture for Modified SUMH. Next we propose a new Hardware-oriented Modified Diamond Search (HMDS) algorithm, along with its co-designed hardware architecture, for fast integer-pel motion estimation in H.264/AVC. Next we propose a new half-pel interpolation filter and modified fractional-pel search algorithm, along with its co-designed hardware architecture, for fractional motion estimation in H.264/AVC. Finally, we combine our proposals for HMDS and fractional-pel search, and pipeline our architecture in order to form a full motion estimator for fast, efficient and low power, motion estimation in H.264/AVC.;Our simulations were done using standard test sequences and the H.264/AVC reference software, while our hardware implementation was done on a field programmable gate array (FPGA). Our results show our proposed algorithms on average, had better speed-up and rate-distortion performance at low bitrates, than previous state-of-the-art fast motion estimation algorithms. In addition, the losses when compared to Full Search motion estimation, are insignificant. Our FPGA-based architecture showed an improvement over previous similar architectures, in terms of power consumption, throughput and area. We also show that its performance in terms of maximum frequency, minimum frequency, equivalent transistor count and power consumption, are comparable to previous architectures implemented as application specific integrated circuits (ASIC). |
