Research Of H.264 Motion Estimation Hardware Accelerator Based On PowerPC

H.264 is a new future IP and wireless environment oriented video compression standard, it is setted up by JV7 which is composed by ISO/IEC and ITU-T. In aspect of the video compression efficiency, H.264 is more better than all others compression standards, however, the encoding technology of H.264 is very complex, computing is more complex than other encoding standards, so the real time encoding is very difficult. Motion estimation is the key technology of video compression encodingm, it shares 60%-80% of the computing in the whole encoding process. At present, there are a variety of motion estimation methods, full search motion estimation algorithm has good forcast effect and the search window data have great relativity, it is easy for hardware implementation, but the requirement of hardware is very high due to the large amount of computing, for fast motion estimation algorithm, it is not necessary to match every position in the search window, that will reduce the amount of computing, but because the date at the match position is anomalous, it can not match multi-position in parallel, that go against to hardare implement. The research object of this article is optimizing the motion estimation algorithm and actualize motion estimation hardware accelerator basing on FPGA.Main work of this paper:(1) Analysis the motion estimation algorithm, optimizing the motion estimation algorithm with the pinciple of reducing the amount of computing and suitable for hardware implementation, bring forward two motion estimation algorithm suitable for hardware implementation, that are sample per pixel search and part full search Under AVC, by using three sequences--foreman, football and news, Compared these two algorithms with full search, with the average reduction on the PSNR is only 0.45dB and 0.67dB, the calculation work can be reduced by 50% and 67.8% respectively.(2) Based on analysing typical motion estimation hardware architecture and with the different applications, raised up speed priority and resource priority hardware architecture.Finished the design of the overall structure and each process module of the hardware accelerator basing on FPGA, and integrated and simulate every module of the hardware accelerator under ISE. (3) Established the minimum PowerPC system on Virtex-II exploited board.Created the IP core of the H.264 motion estimation hardware accelerator and added it to the minimum PowerPC system to complete the hardware accelerator verification platform.Loaded the ture video data for the hardware accelerator. It can get the same results with the motion estimation C code run on PC. So,the motion estimation hardware accelerator that this paper designed can accomplish the data process of H.264 motion estimation.