Research Of Temperature-Aware On-Chip Memory Architechture

In recent years, the VLSI technology promotes the significant improvement of processors’performance. At the same time, we are now facing many new challenges in designing and applying embedded systems, such as high power consumption and soaring chip temperature. While power increases the cost of the system, temperature can even threaten its stability and availability. As there is an interactive relationship between power and temperature, optimization for power without considering thermal issue cannot achieve the best effect. Generally, function units with highly localized activity, like ALUs and register files, are the hottest parts of the chip which have been the focus of thermal optimization. With the shrinkage of feature size, leakage power is increasing dramatically. Even worse, leakage grows exponentially as temperature increases. With high transistor density and the great demand of silicon area, on-chip memory is the dominate contributor of the total leakage. With the absence of temperature management, thermal attacks in instruction caches can result in terrible physical damages. Hence, it is an important problem to handle the thermal issue of memory subsystem on chip.As on-chip memory is introduced to alleviate the speed gap between main memory and CPU, timing performance should always be considered when optimizing power and temperature. In this paper, timing performance and temperature of on-chip memory are both optimized. Many embedded systems are equipped with a hybrid memory architecture that contains both on-chip cache and scratchpad memory (SPM). In this paper, a combination of memory architecture exploration and data allocation is used. In the exploration, memory components of different types, sizes, power, areas and power density are considered.Two memory architecture exploration algorithms and a data allocation algorithm are presented in this paper. All three algorithms limit the continuous working time of cache and SPM by the temperature variation cycle and the capacity. Memory architecture exploration algorithm EBSCR aims to find an architecture with best timing performance while meeting the thermal constraint. As the accessing time of SPM is shorter than cache, in algorithm EBSCR an architecture using SPM most is likely chosen. On the other hand, algorithm EBRou aims to find out the architecture with best thermal behavior while meeting the performance constraint. By analyzing the temperature model, power density is used to estimated temperature variation in algorithm EBRou. A temperature-aware data allocation algorithm TADA is also presented to dynamically map data to memory components at runtime.To evaluate the proposed algorithms, a temperature-aware memory architecture simulation platform is developed. In the simulation platform, an architecture simulation tool SimpleScalar, a temperature model HotSpot, a dynamic power model Wattch and a leakage power model HotLeakage are integrated. The simulation platform is able to analyze the memory architecture by access time, temperature and power. Experimental results show that the proposed algorithm can effectively shorten the execution time, bring down the temperature of the memory components and reduce the leakage power consumption.