| This dissertation presents several topics which are related to temperature-aware and power-aware design.;An efficient unified incremental high-level and physical-level synthesis algorithm was presented in Chapter 2, which enable the tight integration between high-level and physical-level design. Chapter 3 presented a temperature-aware high-level synthesis algorithm built upon the framework of Chapter 2. Temperature variations and hot spots account for reliability issue and require more conservative timing margins, thereby reducing performance. Therefore, reliability-aware synthesis flow was presented in Chapter 4. Recent developments in nanoscale devices open new alternatives for low-power embedded system design. Among these, single-electron tunneling transistors hold the promise of achieving the lowest power consumption. Unfortunately, most analysis of SETs has focused on single devices instead of architectures, making it difficult to determine whether they are appropriate for low-power embedded systems. Therefore, a fault-tolerant hybrid SET/CMOS reconfigurable architecture was presented in Chapter 5. 3D CMOS technology has been developed to overcome the interconnect bottlenecks of 2D design, but at the cost of serious thermal problems due to significant increase of power density by stacking multiple active device layer together. Hence, in Chapter 6, 3D CMP framework was presented and temperature-aware management policy was evaluated built upon this framework. |
