Font Size: a A A

Design Of The Time Keeping System Based On FPGA And SCM

Posted on:2015-02-25Degree:MasterType:Thesis
Country:ChinaCandidate:S Q WuFull Text:PDF
GTID:2268330431954300Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
With the development of the satellite navigation technology, GPS (global positioningsystem) has great influence on more people, once the time basis has deviation or error,itwill cause significant influence to people’s life and production. Based on this case,thispaper has studied to achieve the time keeping system using SCM and FPGA, to provide thehighly accurate time basis for communication and electrical equipments in the case ofstandard clock owing deviation, so that equipments can work normally in the standardclock and plays the role of a backup power. The so-called punctuality concept can maintainthe deviation of its oneself time and the standard time as small as possible. The paper hasdesigned the time keeping system putting GPS/Beidou signal as time basis, the use ofcombination of SCM and FPGA to design the time keeping circuit makes the systemrunning faster, and programming is very simple and can be easy to implement, moreimportant thing is the high precision. The paper mainly introduces each module’s designingand the work principle of the time keeping system, and the hardware circuit and softwareprogram used in the system carries out the detailed analysis and finally describes thedevelopment status and prospect of the time keeping system, this paper launcher theresearch based on this.The research is the designing of the time keeping system based on SCM and FPGA,this paper firstly introduces the main application areas of the designing, explains andanalyzes the current research results and the problems which meets in the research, andthen describes the each module and their function of the time keeping system, mainlyincludes the local clock source, D/A conversion circuit, the counting circuit of FM and PM,the state detection circuit of advancing or lagging, a phase difference detection circuit, thecircuit of advancing pulse processing, the circuit of lagging pulse processing and the circuitof frequency divider, these modules are built to using the simple and integrated circuit withthe characteristics of simple operation and low-cost. Finally, to carry out simulationanalysis of the parts and the whole system, to obtain the waveforms and experimental dataof each module and the whole system after repeated experiments. Finally outputting the time signal with the same frequency and phase of the standard second signal and obtainsthe high-precision time basis, to ensure that can keep this signal after GPS/beidou loss oflock and to achieve time synchronization. The circuits and procedures related to the paperare simulated and verified, obtains the more accurate second signal and can be calibratedquickly in a short time with the characteristic of less error, accuracy can reach107,there issome reference value and good prospect.
Keywords/Search Tags:GPS, time keeping system, FPGA, SCM, time basis
PDF Full Text Request
Related items