Portable Low Frequency Time-Code Receiver Designed And Realized With FPGA

The time service of Low frequency time-code is the most complete informationin the land-based radio time service. It can meet the most people’s requirement ofmedium accuracy. The technology has been used in power distribution systems,electronic commerce systems, electronic government systems, telecommunicationsystems and defense systems. Therefore, it is necessary to study the receiver of lowfrequency time-code.As a starting point to design a portable, high reliability and low power receiverof low frequency time-code which can meet the time accuracy of sub-millisecond.The hardware design and software design of portable low frequency time-codereceiver based on FPGA has been elaborated in the thesis. The receiver ischaracterized by small volume, low power consumption and high integrated. Themain works and contributions can be summarized as follows:z The developing trend of low frequency time-code receiver is discussed,according to the resource consumption of receiver, the thesis choose the FPGA chipof EP3C10E144I7. It has adequate LE, and its stability and reliability can satisfy thedesign requirements.{The hardware design of portable low frequency time-code receiver based onFPGA is elaborated in the thesis. The hardware design include the circuit design ofthe FPGA pins connection, the circuit design of power supply modules, the circuitdesign of the oscillator, the circuit design of DIP switches, the circuit design of theserial converter chip, the circuit design of the FPGA configuration and downloadmodules.|This thesis gives a detail introduction about the software design of thereceiver. Firstly, the whole system design is introduced, and then detailed the moduleof synchronize local second, the module of serial port receive and transmit time code,the module of calculation time code, the module of time keeping respectively, andgives the results of each module.By applying the related results, portable low frequency time-code receiver based on FPGA is finished. Through the system debugging and testing, The resultsshow that: the timing accuracy of the receiver is0to0.7ms, the time keepingaccuracy is sub-millisecond, the receiver can send time-code successfully, thereceiver can meet the design requirements.