Design Of Chopper-stabilized Full Differential Programmable Gain Amplifier Circuit

Sigma-Delta ADC is widely used in various fields because of its high resolution,high reliability and easy integration.As the signal processed by ADC is very weak,the programmable gain amplifier is indispensable in the analog-to-digital conversion,and its performance requirements are very strict.On the one hand,the programmable gain amplifier plays the role to enlarge and transmit signals,and its accuracy directly affects the resolution of the Sigma-Delta ADC;on the other hand,as the input of the modulator module in Sigma-Delta ADC is sample-and-hold circuits,and every time when the clock switches,it will bring severe voltage jitter to the signal channel.Therefore,the programmable gain amplifier must have a strong drive capability,so that the signals can be quickly set up,and the authenticity of the signals can be ensured.To solve the above problems,based on 110 nm CMOS technology,a high performance programmable gain amplifier circuit that is applied to 16bit/10 Msps Sigma-Delta ADC chip is designed in this paper.The circuit is mainly composed of a programmable gain amplifier,buffer and bandgap reference.Among them,the core module is PGA.In the selection of its structure,it applied a fully differential folded cascode structure,enhancing the ability of anti-common mode interference;and in the application of the technology,on the one hand,the chopper and AB push-pull technology was used in the circuit,improving the precision and dynamic performance of the PGA;on the other hand,the current source in the amplifier using self-cascade structure,which can further improve the circuit's voltage margin and robustness.In order to further enhance the drive ability of the PGA output end,a Buffer at the output end of the PGA was added to adapt to the modulator's sampling switch shifting.In addition,the chopper technology was used in this Buffer to reduce its imbalance and the noise,making the signal distortion from the PGA output end to the modulator module small.The basic module in this paper is the BGR,which uses current fusing trimming technology,improving the temperature coefficient of the circuit,and providing precise reference voltage to the common mode feedback circuit of the PGA;meanwhile,the BGR generates the reference current,which can provide reference current for PGA and Buffer to ensure that all circuit can conditionally produce static bias,therefore to guarantee the circuit to work properly.Based on the 110 nm CMOS technology,the Cadence-spectre software is used to simulate the circuit in this paper.The simulation results show that the equivalent inputnoise of PGA is 1.11nV/sqrt(Hz),the offset voltage is 61.5uV,the common mode rejection ratio is 111 dB and the power supply rejection ratio is 107dB;the equivalent input noise of Buffer is 18.6nV/sqrt(Hz),the offset voltage is 27.4uV,the common mode rejection ratio is 126 dB and the power supply rejection ratio is 91.9dB;the temperature coefficient of the BGR is 9.07ppm/?,and the power supply rejection ratio is-97.9dB.The simulation results show that the indexes of each module meet the design requirements,and the comprehensive performance of the overall ADC is good after verified.