The Implementation Of New Memory Burn-in Test System

In recent years, the rapid development of electronic technology has found anincreasingly wide utilization in the application field of integrated circuit. The integrated circuitrelated technology has been widely used in some important fields such as military, aerospace, etc.At the same time, the rising working frequency and the increasing complexity of integrated circuit,make its reliability more and more important. In the reliability test of the integrated circuit, hightemperature dynamic burn-in test is the most important part. The technology that making functionaltest during aging is already used in domestic third/fourth generation integrated circuit aginginstrument.Combining with the new technology of software and hardware, this paper designs and realizesan integrated circuit aging test system based on storage. This system can be used for high speedmemory and some conventional logic devices. This paper introduces the basic principle andarchitecture of aging test system, summarizes the aging system’s signal generation and signaldetection, and makes a brief introduction of several commonly used memories, expounds the basicfault model of memory and some memory testing algorithms. This paper introduces design processof the base board, analog signal board, digital signal board, ARM board, driver board and so on.This paper also makes the detailed analysis and discussion of some important modules such as:waveform generating circuit, waveform detection circuit, drive circuit, the secondary power supplycircuit, ARM and FPGA peripheral circuit.At the same time, the theory of signal integrity andpower integrity have been introduced in the high speed digital circuit design of aging system, andtakes the FPGA and SDRAM data interface of digital signal board as an example to carry onthe pre-simulation and post-simulation on board level, introduces the corresponding constraintlayout process. Then analyzes the aging system from two aspects: the FPGA program (driver)design, the ARM design. The design of FPGA program include: SDRAM driver, A/D and D/Adriver, DDS, etc., introduces the frame format of communication protocol and software runningflow chart of between the ARM and digital signal board/analog signal board. Finally, takes theSRAM as an example to debug the whole hardware and software system, using Signal Tap II(embedded logic analyzer) to analyze important timing signals in design, then make correspondingconclusions.Finally, the work and the disadvantage of this design were mentioned, and the next phase ofthe work was planned.