Research On Key Technology Of Accelerating Cone-beam CT Reconstruction Based On FPGA

Improving the spatial resolution and imaging speed of the Computed Tomography system has been the objective of study and development since it was used for industrial nondestructive detecting and medical diagnosis. As the next generation main CT system, Cone-beam CT has the advantages of isotropy, high spatial resolution and less data acquisition time. But the high performance computing problem of huge amount three-dimensional image data impacts on the overall index of the system performance, limits the development of cone beam CT. Therefore, the technology of accelerating cone-beam CT three-dimensional image reconstruction has become one hot research area in CT domain.With the development of the semiconductor manufacturing process, reconfigurable computing hardware comes into the high-performance computing field. As a hardware that executes parallel in the area space and reconstructs in the time domain, FPGA has become one widely accelerating part of high-performance parallel computing. Aiming at the current cone-beam CT reconstruction algorithm, accelerating three-dimensional image reconstruction is researched based on the latest FPGA hardware structures in this paper. The main contributions are summarized as follows:1. In order to solve the problem that massive data couldn't be storaged in FPGA, a solution strategy for disparting the data is proposed. The strategy includes four steps: data prefetching and―ping-pong‖operation, improving the sequence of voxel cycle, the reasonable solution of boundary effect, block reading. It cause that data can be transfered into FPGA internal blockly, and the data transmission time is hided.2. A CT image reconstruction parallel computing structure based on FPGA is designed. The structure uses the ideas of parallel computing and pipeline technology based on the decomposition of the classic analytic FDK algorithm. Especially in the most time-consuming back-projection unit, double parity dual-port caching mechanism is designed to solve the emerging of―bubble‖. Four interpolating data are taked out in one clock cycle without additional storage resources consuming. No-wait pipeline is achieved. Experimental results show that the structure can obtain higher speedup, and has the characteristic of resource optimization.3. In order to solve the problem that the implementation of the SART algorithm will overload the memory resource in FPGA, a method that reduces storage requirement is proposed. In this method, the effective data to reconstruct a slice will be rearranged. The iteration is only calculated for one slice. The process of slice iteration is achieved. The resource consumption is analyzed. Results show that the slice of 512×512 can be reconstructed in XC5VLX330. 4. A structure that implements SART floating-point algorithm based on FPGA is designed. The structure is designed using pipeline technology, based on decomposition and correlation analysis of SART. Experimental results show that the structure can obtain higher speedup and precision.5. Summarizing the results presented above, a high-performance CT three-dimensional image reconstruction blue print based on FPGA is proposed. From the points of hard core, dynamic reconfiguration, heterogeneous multi-processor and multi-FPGA parallel processing, the blue print is proposed combining the analysis of FDK property and the verification of the experimental results.