Research On Acceleration Of Deep Convolutional Neural Network Based On FPGA

With the boom which deep learning brings about in machine learning field and the advent of the era of big data,convolution neural network has been widely applied to many different application areas,such as image classification,face recognition,object detection and so on.In order to get more powerful ability of features learning and features expressing,the depth of the convolutional neural network model has been in deepening.When real-time,power consumption and extendibility are considered together,the existing general processors CPU or GPU is not able to meet the requirements.Considering FPGA's configuration is flexible and it's characteristics of highly parallel,low power consumption,etc.This subject centers on the acceleration of deep convolutional neural network based on FPGA development platform.In this reaserch subject,parallel and pipeline are focused on to explore the model's accelerating potentials.Some adjustment parameters are proposed to adjust the original computing structure of convolution neural network.In this way,efficient pipeline between adjacent computing layers is formed,and there is less intermediate data that needs to be saved.What's more,some strategies is taken to alleviate the prominent bottleneck in computation,such as the strategy of filtering the padded-elements automatically,the strategy of secondary centralizing accumulation in convolution calculation,etc.The experimental data show that,in the experimental environment of this reaserch subject,while the working clock frequency is 250 MHz,the DSP Blocks occupying about 13% and the image data transmission bandwidth is 0.15 Gbps,for the same convolution neural network model,the computing speed of the implemention based on FPGA is 18.42 times that of CPU,while the system power consumption is less than 30% of the general CPU chip.The experimental results demonstrate that: After adjusting the computing structure,it is more suitable for deep convolution neural network to be implemented on FPGA with good use of parallel and pipeline strategy,the processing speed can be greatly improved and system power can be significantly reduced.Next,the convolutional neural network in deeper and larger scale can be tried to improve it's performance dramatically,in order to meet both requirements of low power consumption and high real-time in complex application scenarios.