High Speed Image Compression Technology Based On Parallel And Pipeline Architecture

High-resolution cameras can improve the spatial precision in aerial and topography field, while high-frame rate cameras enhance the measure precision of moving targets in optoelectronic tracking system. However, the high-resolution camera and the high-frame rate camera generate a mass of data, which is a great challenge for system’s transmission and record in real time. Therefore, the effective image coding algorithms and high-speed coding implementation are fully researched in this paper.The wavelet analysis has became a powerful transform tool in new generation image compression schemes, for its outstanding time-frequency characteristic and multi-resolution analysis ability. The 2D discrete wavelet transform(DWT) can achieve optimal sparse representation for horizontal and vertical directions in image, but suboptimal for the geometric structures of the other directions. In order to improve this weakness of DWT, a adaptive directional hadamard transform is proposed in the paper. This method has low calculation complexity, obtains cheap storage for additional information, and can achieve a better sparse representation performance for images which are rich in geometric structures.Usually, the nowadays wavelet-based image coding algorithms have been developed with coding performance as the primary goal, leading to much more calculational load. The complex coding model and data correlation are the mainly difficulty for those algorithms to implement at high speed. In order to do this in hardware, an efficient adaptive Exp-Glomb coding(EGC) based image coding algorithm and a farther-based block hierarchical indexing coding algorithm are proposed here. Those algorithms has less complexity and can be accomplished in hardware. Based on adaptive EGC coding algorithm, a low complexity image coding method has been designed, which uses several bit planes as a coding path and can generate the embedded bit stream. While the bit stream is transmitted in wireless or other unstable channels, transmission errors will easily happened to affect the decoding image quality. So, a error-resilient image coding algorithm, packing the wavelet subband coefficients as the order of which generated in hardware implementation, is proposed in the paper. Experimental results indicate that the algorithm can resist 1%-2% random errors, and has low calculation complexity, thus can be implemented in hardware.By study of the pipeline and parallel technique in VLSI calculation, several key processing architectures are designed here, including 1D 5/3 DWT architecture, 2D 5/3 DWT architecture, multi-level 2D 5/3 DWT architecture, 2D low frequency prediction module, zero-length coding module and EGC architecture. Optimized using pipeline and parallel technicals and implemented in FPGA, those architectures gains the preferable general performance and bases for high speed image coding implementation in hardware.Finally, employed the calculation modules above, a subband-interleaved image coder and a error-resilient image coder are implemented in FPGA, considering coding speed, hardware resource usage and nonuse of external memory. The image coders are very easy to replant to others platform, for they were designed with the same clock frequency, and parameters of interface, such as image size, bit width, and quantization step and so on, can be set by users. Furthermore, our coders have obvious advantage over others coders reported nowadays in coding spend and hardware resource expense. In project application, the subband-interleaved image coder was employed to achieve high-solution image(10K×10K×2.0fps) coding in real time, with the compress ratio about 10 ~ 30. The coder reduces the image data efficiently when the compression ratio is about 10-30, obtains a good decoding image quality, and meets requirement of project in all aspects.Several low complexity image coding algorithms are proposed in the paper, after deeply studying the image 2D transform and wavelet-based image compression algorithms. Based on the pipeline and parallel technique in VLSI calculation, the subband-interleaved image coder and error-resilient image coder are designed. Finally when implemented in project, it works well and can effectively reduce the pression of transmission and record for high speed image data.