Prototype Design And Implementation Of Parallel Acceleration Experiment Platform Based On FPGA

With the advantage of the Internet of Things and computer technology, the embedded system is developing rapidly in recent years. More and more embedded devices are invented. And these new devices are intelligent and quick response. Then more and more computation is needed. The traditional single embedded processors, which are limited in frequency and computation performance, have been unable to meet the demand. If the multiple processors are used to improve processing performance, the power consumption will be certainly be increased greatly, which is inappropriate for embedded devices with limited energy. In this case, the heterogeneous architecture of Field Programmable Gate Array (FPGA) and embedded processors becomes an ideal solution for solving the problems above. The FPGA acts a co-processor to accelerate the embedded applications.The use of FPGA which works as a co-processor to accelerate specific algorithms is becoming a hot spot in research field. And FPGA-based parallel acceleration models are being proposed more and more. But the algorithms are usually evaluated by simulation and analysis without board-level testing, because the board-level testing needs a large amount of data exchanged rapidly between the main controller and FPGA co-processor. But there are rarely such data exchange platforms. So the high-speed data exchange platforms for parallel acceleration experiment are needed urgently.A parallel acceleration experiment platform prototype is designed and implemented in this paper. The PCI Express bus and DMA is used in order to meet the speed requirement of data exchange. The top-down design pattern is used in the paper. And the platform is divided into a PCI Express endpoint controller module, a PCI Express transaction layer packet processing and DMA control module, a memory controller module, a parallel acceleration experiment module, and an interface module between the parallel acceleration experiment module and the memory controller module. Each module is designed and implemented in details. The PCI Express transaction layer packet processing and DMA controller module is the core module of the entire platform with several sub modules. The parallel sorting algorithm is used as an example in the implementation of parallel acceleration module. Several experiments are done based on the platform implemented above. The experiment results show the actual resource occupation of the platform, the maximum data throughput and the actual parallel speedup. And it is proved that the designed platform can meet the requirements of the parallel acceleration experiments.