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Research Of Image Compression Scheme On The Hardware Based On The FPGA And DSP

Posted on:2015-01-15Degree:MasterType:Thesis
Country:ChinaCandidate:H R WangFull Text:PDF
GTID:2268330428959027Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
Image is the human·s most important information source for its advantages suchas intuitive, lively, easy-to-understand, and can be crammed with much information.Nevertheless, after been digitized, the images contain a huge amount of data, which isnot compatible with most storage device both because of the data transfer rate and thetotal capacity. So the traditional image acquisition system based on the mode ofsensor-image acquisition card-PC cannot meet the needs of practice, the importanceof image compression has grown steadily.Considered that FPGA(Field Programmable Gate Array) has the high processingspeed and the DSP(Digital Signal Processor) is more specific for image coding, thispaper provided a scheme that image acquisition, storage, convertion and the datainterface with the control computer were implemented in the FPGA of the imageacquisition card, and the image compression is applied in the DSP by theJPEG2000(Joint Photographic Expert Group2000) format. On the other hand, inorder to acquire both analog and digital image that arrive at the system, this paper hasdesigned Camera Link interface that comforming to the Camera Link standard andanalog interface for S-video(Super Video) and CVBS(Composite Video BroadcastSigal) format.The image acquisition module is centrolled by FPGA, which simulated the I2CBus connected to the image decoding chip to initialize it. The TVP5150convert thevideo signal to embedded syncs8bit ITU-R BT.6l56format, then the FPGA captureand process the data. At last, the video data stream is transmitted to the DSP processorto encode. The data channel between the system and the control computer is realizedby PCI Bus, the command data and the video data after decoded are both transferredthrough the bus. On the other hand, the image decoder module takes theTMS320DM642of C6000series made by TI company as the key chip to realize theJPEG2000algorithm on the hardware to real-timely compress the image. After debugging and testing the whole system, a lot of improvement has done. Itis proved that the system has a good performance and works stable. Compared withthe original image, the quality loss of the image compressed is not significant. Notonly in the field of industry, but also the science, the system designed in this papershows strong practical and broad application prospects.
Keywords/Search Tags:image compression, JPEG2000, TVP5150, Camera Link interface, PCIbus
PDF Full Text Request
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