Signal Integrity Analysis For High Speed Pcie2.0Serial Bus

With constant breakthroughs in semiconductor technology which have driven the rapid development of a new generation of high speed serial bus, PCIE serial bus with its fast transmission rate and simple system topology has begun to replace the traditional PCI parallel bus in many application fields and it is carried out especially in terms of simplified timing,however, increasing data rate led to the emergence of new problems, new challenges for the signal integrity analysis of serial bus are brought.Signal integrity analysis for high speed serial bus at the rate up to5Ghz need consider more factors which can not be ignored, include dielectric loss、skin effect、 intersymbol interference and various parasitic parameters caused by high speed signal except the traditional reflection, crosstalk. Based on the Stratix IV GX series FPGA development board as a template, using Hspice and HyperLynx as the simulation tools and extracting transmission line S parameter of PCIE2.0card, the whole channel is linked through the backplane and connector. IBIS model and Hspice encrypted model are used. Both simulations generate the receiver eye diagram. By comparison with the PCIE CEM2.0protocol diagram template, based on a6layer board within28inch stripline the receiver eye diagrams after the pre-emphasis and adaptive equalization make full compliance with the the PCIE CEM2.0protocol, providing the reference for the analysis and test of the high-speed serial signal integrity.At the same time, the3.3V PCIE and12V PCIE power integrity are an alyzed in the paper, and the SSN is sampled and simulated by using Hspice.Fi nally, a conclusion can be drawed that the on-chip decoupling is better than th e off-chip decoupling.