Design Of MAC’s Datapath And PCS Based On PCIe2.0

PCIe (Peripheral Component Interconnect Express) is the third generation of high speed serial IO bus, has been widely used in computer and communications systems. The Physical Layer is the lowest level in PCIe which can be subdivided into three layers: MAC layer (Media Access Control). PCS layer (Physical Coding Sublayer) and PMA layer (Physical Media Attachment). MAC and PCS are the parts of the Logical Sub-block which is used to connect the Data Link Layer with PMA and plays an important role in PCIe system. The thesis designs the circuits of MAC’s datapath and PCS which are based on PCIe 2.0 specification. The circuits are compatible with PCIe 1.0 specification and support lx/4x mode. The highest rate is 5GT/s (Giga Transmission per second) and it also supports 2.5GT/s rate.Based on the deeply study of PCIe specification, firstly, the thesis shows the bus level of PCIe, including functions and packet formats of the Transaction Layer, the Data Link Layer and the Physical Layer. Then, the thesis analyzes related technical contents from MAC, PCS and PIPE interface (PHY Interface for the PCIe Architecture). It consists of MAC’s datapath design and PCS design. The MAC’s datapath design can be divided into transmiting pathway and receiving pathway, covering the modules of packet encapsulation and packet dismantling, byte splitting and byte combining, scrambler and descrambler, lane alignment and lane reversal, etc. The PCS design includes 8B/10B encoding and decoding, elastic buffer and power management.In order to verify the results of the circuit designs, the software of modelsim is used to verify each module’s function and interfaces between modules. Then the Design Compiler tool with SMIC 40nm technology is utilized to synthesize RTL code to get Gate-level netlist at 300Mhz. The areas of the MAC and PCS are 0.02 mnrand 0.025 mm2, respectively. The power consumptions are 3.5113 mW and 2.3358mW. In addition, ATLYS development board of the FPGA is taken to analyze resources and verifiy functions. The verification results also satisfy to design requirements.