FPGA-based Communication Signal Channel Detector And Parameter Estimation

With the rapid development of wireless technology recent years, frequency band of electronic countermeasures is becoming more and more wide, forms of electronic countermeasures are becoming more and more complicated, the traditional electronic reconnaissance receiver has been far away form our demands. So, the digital channelized receiver based on software radio idea with the ability of multi-signal processing, large dynamic range, wide instantaneous receive frequency bandwidth, high sensitivity and high resolution arises at this historic moment. The main contents of this paper include:First, the basic theory of channelized recever is introduced. For the problem of the spectrum aliasing between adjacent channels, an Anti-aliasing channelized receiver structure is inferred. The simulation test and data show that this structure is feasible.Then, the detection and parameter estimation of communication signal is discussed. To improve the detection performance, a constant false alarm detection scheme adapted to this project is proposed. Specially, the frequency measurement algorithm of communication signal is studied in depth, which is inferred based on phase measurement and optimized by using CORDIC algotithm. Simulation test shows that this algorithm can achieve the performance index of the project.Also, how to realize the detection and parameter estimation of the channelized communication signal in FPGA is explored. The paper analyzes the problem met in the process of implementation in detail and then proposes the solutions. What’s more, the structure of realization of each module in the project is introduced in detail, which will facilitate the reproducibility of the engineering experiment results.The most important is, high-speed interconnection communication between DSP and FPGA is realized. On the one hand the paper realizes the high rate of data storage and reading using DDR3, studies a variety of DDR3control methdds also analyses and compares these methods,then puts forward some recommendation for use.On the other hand, the paper realizes high-speed interconnection communication between DSP and FPGA using-RapidIO, analyses the method of using IP core RapidIOv5.6and then do the experiments On the hardware platform in the laboratory, the experimental results show that transmission rate can reach3.125Gbaud on single transport stream.