Research Of Reliability Of VDMOS Device In The Vibration Environment

With the advantages of bipolar transistor and common MOS device ofPower VDMOS device has high input impedance, small loss, fast switchingspeed, good frequency characteristic and so on, it is widely used in civil andmilitary, electronic industry, etc. Becsuse vibration environment is importantfactors for product quality and reliability, therefore, it is important to study theinfluence of the reliability of VDMOS device in the vibration environment.Through vibration test and simulation of the distribution of stress of VDMOSdevice by ANSYS finite element software, device is studied for failuremechanism.Variable frequency and constant frequency vibration tests are used in threedifferent types of VDMOS device by using electric vibration table. XJ4832high-power semiconductor curve tracer is used in the measurement of VDS-IDcharacteristics of device, electron microscope is used in the observing the changeof device shell and internal chip surface; ANSYS finite element simulationsoftware is used to set up three-dimensional model of power VDMOS device, thedistribution of vibration stress of devices is simulated in vibration conditions,failure mode and mechanism of device is analyzed.The experimental results demonstrate that: under the condition of variablefrequency vibration, when the corresponding stress of the vibration frequencyreaches fracture strength of internal material of the device, IDSof three kinds ofmodels are all reduced by more than20%of the initial value; under the conditionof constant frequency vibration, when the vibration stress is close but do notreach to the breaking strength of the device, along with the increasing of time ofconstant frequency vibration, the device of three kinds of models will also causeddegradation of VDS-IDbecause of vibration fatigue. Vibration makes layers ofsingle cell of device produce strain, with the change of vibration frequency andtime, when the strain reaches to the fracture strength of material, micro-cracks are produced on chip, and gradually spreaded to many single cells, at the sametime, pins are easy to break, leading to degradation of VDS-IDcharacteristics ofdevice. When VDS-IDfeatures of VDMOS device in vibration environment istested, because the applied voltage compared with their own limits voltage ofVDMOS of three models is very small, so the applied voltage will not affect VDS-IDfeatures of VDMOS device.The results of the simulation demonstrates that: the boundary of the chipand existing empty bonding layer, corresponding stress of the chip of emptyspace is bigger, the stress leads bonding layer to micro deformation, and chip tomicro crack; fatigue fracture happens easily under the repeated actions ofvibration stress in the external pin. It is consistent with the experimental resultsand the results of experiment and simulation provide theoretical and experimentalbasis for reliability of VDMOS device.