Research On Degradation Mechanism Of SiC VDMOS Under High Temperature And Dynamic Gate Pressure

Due to its low conduction loss,high breakdown voltage and high power density,SiC-based VDMOS has a wide range of applications in power electronic systems.However,due to the high temperature and high gate voltage in the working environment for a long time,this may cause problems such as increased on-resistance or increased offcurrent.The current research is limited to the degradation mechanism and model under static gate stress,and the research on dynamic gate stress that is more instructive for the practical application of the device has not been fully developed.The purpose of this thesis is to reveal the degradation mechanism of SiC-based VDMOS devices under dynamic gate stress and establish a degenerate lifetime model with related parameters.Firstly,through the combination of computer simulation and theoretical analysis,the sub-threshold I-V curve method,CV curve method and CP current method for SiC device interface damage and oxide charge injection characterization are studied and demonstrated.Secondly,dynamic gate stress is divided into high-level stress phase,zero-level stress phase and transient stress phase,and the influence of different dynamic gate stress conditions on device degradation is studied.It is found that in the high-stress phase,the increase of the interface state density and the charge trapped in the oxide traps cause a constant drift of the threshold voltage with the stress time,and both the high temperature and the high pressure accelerate the formation of the interface state and and activate more gate oxide traps;The charge back trap effect during zero-stress phase restores the threshold voltage degradation,and the recovery speed decreases with increasing temperature;There is no essential difference between the transient stress phase and the high-level stress phase on the degradation,and the gate pulse frequency and rising or falling edge time have no obvious influence on the device degradation rate.Based on the above conclusions,the modeling ideas and methods for the device lifetime model under dynamic gate stress are proposed,and the lifetime prediction model of threshold voltage Vth for SiC-based VDMOS devices under dynamic gate stress is established.Based on the above research conclusions,the modeling ideas and methods of device lifetime model under dynamic gate stress are proposed,and the lifetime prediction model of threshold voltage Vth of SiC-based VDMOS devices under dynamic gate stress is established whose error is less than 15% compared with the test results.The dynamic gate stress degradation mechanism and related life model disclosed in this paper provide some theoretical guidance for the life assessment and reliability of SiC-based VDMOS devices in industry.