Optimized Design Of A 600V Planar Gate VDMOS With High UIS Performance

VDMOS is the core of semiconductor device which manage electric energy,and it has been widely applied in automotive electronics,consumer electronics and aerospace field owe to it's excellent electrical characteristics and low cost.However,foreign semiconductor companies monopolize the high technology market of VDMOS.The domestic VDMOS is in the backward technology,especially the poor tolerance of the avalanche ability.The theoretical research about tolerance of avalanche is comparative mature at present,however,it is remain very difficult to present a reasonable,cheap-to-make scheme.The main contents of this paper are as follows:The work of this paper is based on a mature technology platform of a well-known domestic semiconductor foundry.The main subject of this thesis is to design a 600 V VDMOS,which has high ability of avalanche tolerance,hoping to help promote the localization of high-performace VOMOS.Firstly,the basic theory on design VDMOS and the method of improve the ability of avalanche tolerance were studied.There are several kinds of structures has been researched,the appropriate structure of cellular and terminalation is selected,then based on the actural technology platform to design the process.With the help of Tsuprem4/Medici,simulate and optimize the process steps and device parameters of cellular part to meet the requirements of the project partners.Based on study of the influence factor of avalanche tolerance,a new H-shaped contact layout design has been provided to improve the ability of avalanche tolerance.Secondly,Simulate and optimize the terminal structure of VDMOS.At first,the JTE structure has been adopted and optimized to get the result that the peak electric field is less than 2×10~5 V/cm with the help of Tsuprem4/Medici.Then,an advanced process technology of high temperature driving has been applied in the design of VLD structure.In addition,it gets a better result that the peak electric field is less than1.8×10~5 V/cm and has a more stability of the breakdown.Finally,the software Candence is used to finish the layout and tape-out.Test the static characteristics and the IAS of samples.The results of first taping out show that,the BV is higher than 640 V,the Vth is about 3V,and the Ron is about 1.75 ?,but the IAS is below 0.1A.Thereafter,the process flow is optimized,tape out again.Test the samples of second taping out,the results show the IAS of two different cellular structure are 2.1A and 2.5A,respectively.The IAS has been greatly improved by means of optimize the process flow and layout design.