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Process Research On 6-inch High Performance Silicon Epitaxial Materials For Power VDMOS Devices

Posted on:2018-10-10Degree:MasterType:Thesis
Country:ChinaCandidate:B XueFull Text:PDF
GTID:2348330542477439Subject:Electronic and communication engineering
Abstract/Summary:PDF Full Text Request
As a new generation of high power semiconductor devices,VDMOS has the advantages of both bipolar transistor and common MOS device,is the ideal power device.The current is to high pressure,high frequency,high current,low power consumption direction.But as the growth of the epitaxial size,the thickness of epitaxial surge,epitaxial wafer in thickness uniformity,the resistivity of control difficulty increasing,the epitaxial transitional section,the integrity of the lattice control problems cannot meet the requirements at the same time,thus caused the domestic production of silicon epitaxial wafer quality cannot fully meet the requirements of VDMOS device is more and more severe,causing a year need a lot of procurement from abroad,the status quo,always face the plight of others.In this paper,we researched the relationship between the epitaxial process with the lattice structure of epitaxial material,the thickness,the resistivity and their uniformity,and the longitudinal resistivity distribution,by also we produced 6 inch silicon epitaxial wafer for the realizing large,high-performance VDMOS by using the LPE-3061 D pan cake epitaxial device.During the experiment,we researched the influence of the silicon epitaxial film deposit rate,process temperature,the gas flow field and the thermal field to the thickness,resistivity uniformity and the integrity of the silicon epitaxial film lattice.And by using the controlling method of the gas flow field,the thermal field,the thin film process of the susceptor,the gas purge method of the reactor system,the rapid growing method of the silicon intrinsic film and the two steps of the deposit process,the uniformity and the stabilization of the silicon film parameters have been improved very obviously,the thickness,the resistivity uniformity and the silicon epitaxial film lattice structure are all well.Finally in this paper,through process optimization,the preparation of 6 inches between the piece and piece of silicon epitaxial wafer thickness nonuniformity is less than 1%,the resistivity inhomogeneity is less than 1%,the surface is light,no dislocations,dislocation,fog,and slip line defects,the width of transition zone for(3 ~ 4)microns,meeting the requirements of the VDMOS device of silicon epitaxial material.
Keywords/Search Tags:VDMOS, Chemical vapor deposition, Non-active doping, Transition region, Epitaxial layer
PDF Full Text Request
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