Research Into Degradation Mechanisms And Lifetime Model For SiC VDMOS Under UIS Stress

Silicon carbide vertical double-diffused metal oxide semiconductor transistor(SiC VDMOS) has been used in a variety of power conversion systems because of its high blocking voltage and switching speed, as well as low on-state resistance and switching losses. The undamped inductive switching(UIS) process is the extreme electrical stress that a VDMOS frequently endured in the application system. The long-term UIS operations will gradually degrade the device electrical parameters, and it has become an important factor to influence the lifetime of device.Therefore, it is urgent to study the degradation mechanisms and lifetime model of SiC VDMOS under UIS stress.In this thesis, the electrical parameters degradation mechanisms of the SiC VDMOS under repetitive UIS stress was firstly studied based on the T-CAD simulation platform and ?/? test system as well as the charge pumping and capacitance-voltage methods. It showed that hot holes injection into the field oxide above the JFET region resulted in the decrease of threshold voltage(FTH) and the increase of off-state drain-source leakage current(IDSS), at the same time, it also lead to the decrease of on-state resistance(RON) at the initial stress. However, with the increase of stress time, the resistance was increased finally under the influence of metal fatigue and stacking faults in epi-layer. After that, the influences of different UIS test conditions (including junction temperature of the device, peak current of UIS stress, element parameters of the circuit model etc), on the electrical parameters degradation of the device were studied in detail, then three kinds of device structures to improve the UIS reliability of the SiC VDMOS have been brought forward, including the device with step gate oxide, the device with shallow P-well and the device with shallow P-top structure. Finally, the lifetime prediction models of VTH and RON based on the degradation mechanisms under UIS stress were put forward respectively.The verification results show that the presented lifetime models of SiC VDMOS under UIS stress can predict the degradation tendencies of VTH and RON very well, and the model errors arc smaller than 10%.The degradation mechanisms and lifetime models of SiC VDMOS under repetitive UIS stress revealed in this thesis can provide theoretical basis for the development of SiC VDMOS with high reliability.