Small Area And High Performance AES/SMS4/DES IP Multiplexing Circuit Design For Mobile Payment

With the rapid development of mobile payment industry, how to ensure information security becomes more and more significant. The password techniques to protect information security is very important. National commercial password management office released the SMS4 symmetric cryptographic algorithmin which used in Wireless local area network(LAN) products In January 2006, it is the first commercial cryptographic algorithm Domestic official released, greatly promote the process of development and localization of cipher algorithm research. Advanced encryption standard(AES) was a new type of security encryption standard released at the beginning of the 21 st century.As the AES is the replacement of DES, From being accepted as the standard, it has already been banking administrative department and the industry as the DE facto standard password.The rapid development of the symmetrical password led to the two problems, One is the upgrade products compatible with the old algorithm, the other is based on the security of the application environment choicing different algorithms.In order to solve these two problems, this paper realize SMS4/AES/DES algorithm IP reuse circuit. Not only supports a variety of algorithm and has the advantages of small size and high performance.For the common characteristic of the iteration computation of the SMS4 algorithm, AES algorithm and the DES algorithm, reused the circuit loop iteration of the above algorithms. For the sboxes of AES algorithm and SMS4 algorithm are both based on the multiplication inversing and affine mapping calculation, reused the sboxes of the above algorithm. And because the symmetric encryption/decryption algorithm apply a round key each round, adopt the style of the round key generation to dynamical generation style, in the other words, generate the current round key during the current round. The traditional way of the round key generation is the round key precomputation way, namely all the round keys are computed before the crypto-operation and stored in RAM, At every round of operation will the current round key be fetched out. compared with the traditional round key precomputation way, the round key dynamic generation way save the area of RAM, the encryption process can begin encryption without waiting for all round key generation finished.In this paper, every circuit design was implemented by Xilinx Virtex-6 FPGA. Compare with latest researches, consuming less area, the throughput of AES, SMS4, DES and IP multiplexing circuit in this paper can reach 2.04Gbps?3.37Gbps?2.68Gbps?1.21 Gbps. Every design was verificated based on Xilinx KC705 development board.This paper also implemented every circuit design for ASIC implementation based on SMIC 130 nm CMOS standard cell library. Comparison with latest researches, with using smaller aera, the throughput of AES, SMS4, DES and IP multiplexing circuit in this paper can reach 1.98Gbps?3.35Gbps?0.38Gbps?1.15 Gbps. Finally, this paper completed AISC backend design flow for IP multiplexing circuit.