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Analysis And Implementation Of SMS4 Algorithm

Posted on:2007-12-29Degree:MasterType:Thesis
Country:ChinaCandidate:X X ZhaoFull Text:PDF
GTID:2178360182486884Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
As national economy and society informational, information security is drawing more and more attention. Cryptography is the crucial technique in the information security field, so research on it becomes even more important and exigent.SMS4 algorithm is the domestic encryption standard released for WLAN use. The thesis analyzed the structure of SMS4 algorithm, and proposed several hardware-implementation methods according to different encryption modes, which are full-loop structure, loop-unrolling structure, pipelined-structure, and loop-unrolling& pipelined mixed structure. The FPGA implementation is also introduced in this paper: (1) Full-loop implementation;(2) Pipelined implementation;(3) High-speed engine implementation.Implementation 1: SMS4 is a 32-round iteration algorithm, so a full-loop structure is proposed as the first method. It not only costs less cell consumption, but also can be used in the feedback mode, like CBC,CFB, OFB. The main disadvantage is that for each data block 32 rounds calculation are needed, which limits the data throughput and system frequency.Implementation 2: The second method is a pipelined structure. Two concrete ways are proposed according to different s-box implementations. One is using LUT, the other is using ROM. Pipeline is the most popular technique to improve the performance in digital IC design. More than one data block are calculated parallel simultaneously, which greatly accelerates the calculation speed. However, this method cost too much and can not realize modes like CBC,CFB, OFB.Implementation 3: In this paper, an inner-round pipelined, high-speed engine is proposed after analyzing the features of this algorithm. By using pipelined or parallel multi-engines, throughput and hardware cost can be easily adjusted according to different applications. Compared with the 32-stage pipelined structure, hardware cost is much lower under the same throughput.Simulation and synthesis results of these implementations are also discussed in this thesis.
Keywords/Search Tags:SMS4, Cryptography, FPGA, pipeline, Engine
PDF Full Text Request
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