The Design Of Reshape Chip Based On Openrisc

Since the first Integrated Circuit was invented by a famous company inAmerica-TI, Integrated Circuit‘s scale and related techniques have been developingrapidly. The most obvious phenomenon is that the number of transistors combined in aprocessor is becoming larger and larger, while the processor is becoming smaller andsmaller. Although the transistors‘number in the processor is doubled every18months,as described in Moore‘s Law, the processor‘s performance is not doubled. The maincause behind this phenomenon is that the processor‘s energy budget is certain, andthis certain energy budget is unable to provide the needed energy when most of theprocessor‘s transistors operate simultaneously, which eventually result in―Utilization"and―Power Dissipation" problems. In the field of mobile devices, theprocessor‘s usable energy is more limited, which causes the energy budget to be themain factor that limit the performance of mobile devices.Currently, there are two ways to solve―Utilization"and―Power Dissipation"problems. One is to customize ASIC according to requirements. This methods issimple and effective, but has an apparent defect, which is that only certain softwarescan run on ASIC. Even minor upgrades on these certain softwares may result in thechip‘s scrap. Therefore, the frequent upgrades of current softwares largely increaseusers‘cost. The other way is to design hardware accelerator for certain fields. Thismethod apparently increases the processor‘s power usage efficiency. The upgrade ofsoftwares will not reduce the processor‘s performance substantially. Besides, theprocessor can also run general programs. According to these advantages, I come upwith a general processor‘s architecture design based on hardware accelerator.In order to design the general processor architecture, two main problems must besolved firstly. The first problem is how to make sure that the kinds and number ofaccelerators that are needed to be integrated in the chip have covered corresponding applications‘to the biggest extent. The second problem is how to chooseprogramming model, that is, in what way the numerous accelerators are integrated inthe chips and how to use them to make programs more effective. In order to solvethese two problems, we will design a brand new multi-accelerator architecture tomake a balance between performance and energy cost in certain fields, to increase thecoverage of accelerators in applications while ensuring the simplicity and reliability ofprogramming models and to reach a satisfactory accelerator ratio in order to solve―Utilization"and―Power Dissipation" problems.Considering that Openrisc is an open-source CPU architecture, and has acomplete tool-chain, I choose Openrisc as the core processor of the whole SoC. In thispaper, I studied the heart of Opentrisc, the data and instructions‘cache, the data andinstructions‘MMU, the programmable interrupt controller, the timer, the powermodule,the debugging module, the Wishbone bus, and so on. Then I come up with IPkernel design based on FFT algorithm, and introduce IP kernel‘s structure, functionaltest, on board test, speed-up ratio, and so on. Eventually, I come to the conclusion thatusing the same CPU architecture, if you run the same algorithm, the CPU with FFT IPkernel‘s runtime is much more shorter than the CPU without FFT IP kernel‘s runtime.Thus, we are able to reduce the CPU‘s dissipation by shortening CPU‘s runtime of thesame code. In the later period, we cope the IP kernel and Openrisc in a desirable way,and distinguish the code segments which are fit for speedup in order to make full useof accelerators most efficiently. In this way, there is no need for programmers to knowhardware architecture, and they can write coded according to actual needs.