Design And Implementation For Highly Parallel Finite Impulse Response Filter And Fast Fourier Transform

Highly parallel Finite Impulse Response(FIR)filter and highly parallel Fast Fourier Transform(FFT)are widely used in many high-throuput low-latency applications such as optical communication,radar and electronic countermeasure systems.Those modules occupy large chip areas and high power dissipations due to their numerous multiplications and additions,high clock frequency and high switching activity.The prospective digital signal processing applications,including tele-medicine,augmented reality and ultra-high definition video,will demand high processing throughputs,large data teansmission rates,rigorous latency and low power consumptions.Therefore it has a great importance to investigate the high-efficiency low-complexity implementation methods for highly parallel FIRs and FFTs designs.To satisfy the demands for low-complexity and high-efficiency highly parallel FIRs and FFTs,this thesis proposes a variety of methods at algorithmic and arithmetic level.The contributions of this thesis are summarized as follows,for parallel FIRs:(?)a 16-parallel and 2k-parallel fast FIR algorithm are proposed,which can save[1-(3/4)k×100%of multipications compared with direct implementation.And an improved hardware structure to support time-varying coefficient FIR filtering is presented;(?)a novel low-complexity algorithm for prime-number-parallel FIR(which called Low-complexity Prime-number-parallel FIR,LPF)is proposed,which can save more than 40%of multipliers for an N-tap L-parallel FIR where L is prime;(?)a low-complexity implementation method for short-length highly-parallel FIR is designed,which utilizes the unfolding method to duplicate a small parallism FIR to design the highly-parallel FIR;And for highly parallel FFTs:(?)at algorithmic level,this thesis analyzes the rotation complexities of Cooley-Tukey Algorithm with different factorization methods for 2k-point FFT,which found that the flow graphes of different factorization methods only differ in the values and locations of rotations.Besides the hardware complexity of rotations can be minimized by choosing two balanced radixes in each factorization;(?)at arithmetic level,a novel high-throughput FFT design strategy which employs bit-serial arithmetic units to implement the multipliers and adders in a highly parallel or even a fully parallel FFT structure is presented.Benefit from the fully parallel scheme,the data addressing and routing are easily implemented by direct wire connection.The proposed fully parallel 512-point FFT processor can achieve 16GSps throughput with 1554K equivalent gates under SMIC 65nm technology,which has a hurge promotion in throughput and speed-area ratio compared with existing works.