Research And Design Of Low Latency Digital Signal Processing Unit

For the existing real-time electronic reconnaissance system,it is hoped that the processing time of the reconnaissance algorithm is short enough,and the hardware cost required for the algorithm implementation is as small as possible.It is urgent to explore new design methods and theoretically to obtain an optimized implementation structure.For example,the DFT calculation unit commonly used in real-time reconnaissance systems requires that the calculation result has as little clock latency as possible so that the system can respond quickly.In order to do this,a parallel processing structure must be adopted.At present,the algorithm structure based on the binary system still needs more than 50 clock cycles when completing 256-point processing;in typical signal processing such as long-point and two-dimensional DFT,adaptive filtering,etc.The throughput and clock latency have similar requirements,so a new computational unit with low complexity and high speed processing is needed for optimal design.On the other hand,in the design of high-speed digital filters,combined with the parallel processing structure of the filter and the high-precision and low-complexity characteristics of algebraic integers,the system design complexity and processing speed can be simplified.The reduction in processing delay and the increase in computing speed will bring significant technical advantages and better system performance to systems such as electronic reconnaissance.This paper combines the actual needs of electronic processing,real-time detection and other information processing systems,starting from the basic unit of digital signal processing,with high-speed,low-complexity FFT and FIR typical digital signal processing unit as the final design goal,to study the basics involved in this process.Theory,key technologies and design methods are proposed to provide a new technical route in high-speed,low-latency,low-complexity digital signal processing methods and implementation structures.This paper first uses MATLAB and other tools to complete the algorithm fixed-point simulation,and then based on the FPGA verification platform.Functional and performance verification.The main work of this paper is as follows:(1)Start the FFT calculation unit to shorten the calculation latency,study the optimization structure compatible with different points FFT operation,and give the implementation structure of the algorithm design and engineering.(2)Starting from the FIR calculation unit to shorten the calculation latency,study the optimization structure of FIR operation with different parallelisms of different orders,and give the implementation structure of the algorithm design and engineering.(3)Based on the Xilinx K7325T ffg900-2 development platform,the simulation demonstration system based on fixed-point simulation,RTL design and simulation,and FPGA-oriented hardware test is designed to calculate the throughput rate and calculation delay of the basic calculation unit of digital signal processing.Performance evaluation was performed on resource occupancy and the like.The high-speed digital signal processing unit proposed in this paper takes the high throughput and low latency as the core of the research,and reduces the number of multiplications by algorithm transformation to reduce the hardware complexity.The key to this paper is to meet the computational delay requirements of the hardware resource occupancy constraints and operating speed requirements.According to the operation speed of 200Mhz,the 256-point FFT calculation unit calculates the lag time as only 85ns,the throughput is up to 12.5Gsps,the 64-order FIR calculation unit has a latency of 9 clocks,the 32-order FIR calculation unit has a latency of 5 clocks,and the throughput is up to 3.125Gsps.