Hardened Design And Implement Of Processor Core And Memory Controller Of A Homogenerous Quad-core Chip

As computer technology and microelectronics technology are developingcontinuously, aerospace grade processor is applied frequently in spaceborne andaerospace system. RAD_X processor is such a space level isomorphic quad-core chipdesigned and realized independently by our university. Specific consideration should begiven to circuit design while designing aerospace-chip. In order to avoid space radiationaffect circuit. This article focuses on the demand for anti-radiation of several importantunits in RAD_X processor. It designs and realizes a variety of hardened circuits.Based on the0.13um CMOS technology, this project implements comprehensivelogic design and verification of the processor core components, adopting thesemi-custom design flow. It also completes logic synthesis and post-simulation task.The main content and the results of the work of the article include the following aspects:Complex space radiation environment is primarily studied and analysized.Moreover, several radiation effects affecting the reliability of the chip are summarized.On the basis of SPARC V8architecture and focusing on SEU impact，hardened designstrategy of RAD_X structure level is brought up.According to the structural features of pipelined stack registers and register file inthe kernel integer unit and the anti-radiation demands, Methods of triple redundancymodular to harden pipelined stack registers and extended hamming code to hardenregister file are raised. The logic realization and reliability verification are also carriedout.Based on the overall structure characteristics of the cache system, the projectproposed the method of block parity check codes to validate its data and to update errordata via data reloading. The logic implementation and reliability verification areconducted as well.According to the structural features of the memory controller and the anti-radiationdemands, the method of bch codes to harden memory controller are raised. The logicrealization and reliability verification are also carried out.After post-simulation and FPGA verification, the radiation consolidating designfunctions made in this article is proved correct. The operating frequency of chip canreach100MHz. Theoretical analysis shows that the breakdown rate of the chip dropsfrom0.4596error/equipment a day to2.161195e-8errors/equipment a day. These normscompletely achieved the pre-specified performance.