Design And Implementation Of L1D Cache For X-DSP

With the development of integrated circuit technology, the performance enhance ofDSP is faced with severe “Memory Wall” problem.“Cache+RAM” memorystructure is an important way to slove this problem. Design an efficient, flexible firstlevel Data Cache (L1D Cache) has an important role to improve the DSP efficiency andoverall performance.X-DSP is a32bits high-performance DSP, which is developed by the NationalUniversity of Defense Technology. It adopts very long instruction word (VLIW)structure and supports two parallel Load/Store accessing. X-DSP uses two levelsmemory hierarchy. The first level memory includes L1P Cache and L1D Cache, thesecond level memory is shared memory and can be configured as L2Cache/RAM. Thispaper focuses on the design and implementation of L1D Cache. The main works includeseveral aspects as followng:1. Based on the analysis of the overall structure of the X-DSP and its memoryhierarchy design requirements, a capacity configurable L1D Cache is designed andrealized. It uses the two-way set associative rule, pseudo LRU replacement algorithm,writing back with not writing allocation strategy and supports two-way parallelaccessing.2. A Cache coherence maintenance mechanism in combination with hardware andsoftware is put forward. On one hand, when DMA reads or writes data to L2RAM, theL1D Cache maintains the data coherence by supporting the snoop from L2SRAM. Onthe other hand, L1D Cache provides lots of control registers for programmer to writeback or write back with invalidation of the L1D Cacheline globally or partially.Moreover, a memory protection mechanism is implemented, which ensures that only therequests meetting the configuration permissions can access the memory space and thecontrol registers.3. This paper proposes a method to solve a cross-border unaligned access forX-DSP by splitting it into two aligned accesses with high efficiency and low hardwarecost, which does not increase the additional burden on the compiler.4. A accessing pipeline and a miss processing pipeline are designed andimplemented for L1D Cache to deal with the hit and miss of Load/Store instructions. Inorder to process the write misses, a128bits width and4depth writing miss buffer withmerging function is designed, which can reduce the waiting delay of the writing misseffectively.Finally, the functional verification in module level and logic synthesis of the L1DCache have been done. The experimentation results show that the function of L1DCache is correct and the work frequency has reached up to1GHz. The L1D Cache meets the design requirement of X-DSP.