Research On Parallel Processing In Gray Scale Image Template Matching Based On FPGA

Template matching is widely used in the field of image and signal processing. And the rapid development in science and technology makes the processing scale of image template matching become larger and larger, in the meanwhile, the more outstanding challenge is that people’s demand of real-time image processing also becomes higher and higher. Therefore, by using general-purpose processor to achieve real-time image template matching, the speed has become the bottleneck. In addition, some excellent algorithms can be executed normally on desktop and workstation,but when they are applied in embedded systems, due to the speed and resource constraints, the effect of simplified algorithms are unacceptable and even some of them can’t be normally operated. Programmable logic gate array is a kind of programmable and powerful logic device, and its high flexibility,easy configuration, cost-effective and supporting parallel and pipeline system design make it become an ideal platform for real-time image processing field. Therefore, in the case of resource constraints, the FPGA can be applied in real-time image template matching to realize image parallerl processing.Firstly, the characteristics of traditional template matching based on sliding window is analyzed and it finds that the traditional template matching based on sliding window is a serial fourfold cyclic process; moreover,the basic concept of FPGA and its design method and parallel processing technology are also analyzed. After that, four parallel processing measures of image template matching based on partition strategy are presented. The four strategies including:the image is not separated and so is the template, the image is separated and the template is not, the image is not separated and the template is, the image is separated and so is the template. Secondly, with regard to the four parallel processing measures of image template matching based on partition strategy, their time complexity and implementation complexity are researched and analyzed. By comparing and analyzing the advantages and disadvantages of the four parallel processing measures, the strategy of the image is not separated and the template is is chosen to solve the problem of the acceleration in image template matching. Based on the strategic, the system Structure& Operation theory of the binary image template matching using parallel processing is analyzed and designed, and a binary image template matching parallel processing model based on FPGA is proposed, this model includes three parts:sub-template division, parallel processing, and global matching. Then, in order to apply the proposed model to gray scale image template matching, the RS232serial communication and the bimodal histogram binarization based on FPGA are designed and implemented. After getting the binary image, the binary image template matching parallel processing model based on FPGA is realized through hardware circuit and VHDL language.Finally, the waveform simulation for each function module and the whole system are did, then synthesizes the VHDL code into ISE9.2and implements it on FPGA. After comparing and analyzing the experimental result and the outcome operated on PC, the results show that the gray scale image template matching based on the FPGA has a well acceleration ratio.