All-Optical Programmable Logic Array Based On Canonical Logic Units

Programmable logic array (PLA) is a kind of programmable logic devices used to implement combinational logic functions defined by users, showing advantages of flexible configuration, high integration, high processing speed and high reliability, andit has a very wide range of applications in the electric field. While in the optical domain, although the elementary logic gates have been developedrelatively mature and have great potential for applications in network node header detection, optical routing, optical label switching and other signal processing, for more complex logic functions, a simple and reconfigurable solution is also required to increase the possibility of their use in high-performance computing and optical networks. All-optical programmable logic array is a good solution.In this thesis, based on a detailed analysis of the recent research status and problems of all-optical programmable logic array, we propose anall-optical programmable logic array using canonical logic units (CLUs-PLA). The main achievements are listed as follows.(1) The characteristics and properties of the canonical logic units (CLUs) are introducted in detail and we propose a concept that the canonical logic units can be regarded as a set of bases of combinational logic functions, thus, any combinational logic functions can be realized by applying these bases. The configuration and function of each part of programmable logic array is either given in detail. According to the analysis, the most crucial chanllege the optical PLA faced to is that the OR array is difficult to demonstrate in an optical way. Based on the characteristics of CLUs, a CLUs-PLA is proposed to solve this problem. Compared with traditional PLA, the input circuit of CLUs-PLA can be realized by only a single passive DI, theCLUs array substitutes for the AND array and the OR array is no longer requiredsince the CLUs can be coupled directly. Therefore, how to achieve CLUs in a simple and efficient way becomes the key to realize CLUs-PLA.(2) The implementation of CLUs is investigated with the cross-gain modulation in SOA and the configuration of SOA cascaded by tunable bandpass filter. Details of the SOA theoretical model used in ourresearch are presented.The model takes into account the carrier heating and spectral hole burning, making it more suitable for high-speed signal processing. Meanwhile, the system structure of SOA and cascaded filter is also analyzed numerically,and the results verify the feasibility of using this method to achieve canonical logic units. Then, the full sets of two-input and three-input CLUs are experim entallydemonstratedwith a bitrate of40Gb/s, and maxtremscan be abtained by minterms. Subsequently, the program is extended to four inputs and the corresponding CLUs are successfully achieved. The program showsgreat reconfigurability and serial scalability. Depending on different conversionsof logic expressions, the scheme can be extended by differnentcascadingconfigurations.(3) The CLUs are analyzed with a SOA-Sagnac interferometer and the cross-phase modulation effect in SOA. The SOA-Sagnac loop is simulated with anequivalent configuration andinvesgated numerically.Three-input OR and NOR operations are numerically realized, showing thecapability of the program to achieve CLUs.Based on the simulation results, two/three-input logic OR and NORoperationsare experimentallywith a bitrate of20Gb/s first.Afterwards,the modulation speed is increased to the42Gb/s, and three-input CLUs are successfully achievedwith the combination of optical input circuit. To the best of our knowledge, thisis the first time that logic operations with more than two inputs areexperimentally demonstrated at high speed in such a scheme.The program operates in a parallel mode. Minterm unit and maxterm unit can be achieved simultaneouslyat the two outputsof the loop and CLUs with more inputs can be generated by increasing the number of control signals directly.(4) Multi-input/outputCLUs are investigated with the four-wave minxing in HNLF. With the Split-step Fourier Method, HNLF is simulated and40Gb/s multi-input/output AND logic units are numerically realizedwith three RZ signals.Three-input and two-input logic AND operations are simultaneously achieved in nine different channels. Then, combined with the optical input circuit, two-input and three-input CLUs are simultaneously achieved in five different channels with an operation speed of40Gb/s. Based on the experimental results, we proposed an expanded CLUs-PLAand the computing capacity is defined and discussed in detail.For a three-input O-PLA, the computing capacity of the expanded CLUs-PLA is two and a half times as large as that of the standard CLUs-PLA, and this multiple will increase3.6as the idlers are individually independent.(5) With the CLUs-PLA, several important combinational logic functions are experimentally demonstrated, including40Gb/s full adder, full subtractor and4-to-2 priority encoder. In addition, optical binary multiplier is proposed using CLUs-PLA, and a2-bit multiplier is numerically demonstrated. The logic patterns are correct and all the temporal waveforms are clean and clear without any pattern effect. The simulation results indicate the feasibility of implementing multiplication in the optical domain. In conclusion, all the results show that it is feasible to demonstrate a programmable logic array by using canonical logic units, and CLUs-PLA can be reconfigured toperform different combinational logic functions.