Research On The Fault-Tolerant Technology Of The Joint Servo Controller Based-FPGA

With the rapid development of computer technology and large-scale integrated circuits, the increasing complexity in the design of controller bring new challenges to the reliability of the system while improving performance. As to the joint controller of robot, how to realize maximum fault-tolerant ability under limited resources and a demanded performance at the same times will be the topic disussed in this paper.This paper studied the fault-tolerant technology under the reliability requirement of the joint controller in 6-DOF robot. It analyzed the basic types of redundant structure, and studied the reliability of redundant system using Markov model, presented a solution of the dynamic dual-controller redundant fault-tolerant system. At the same time, this paper solve single point fault on system with NMR system. And designed a multi-mode redundant self reconstructing, self check judge circuit to realize critical part's fault handing, avoid introducing extern signal flexibility. Finally, it gave specific circuits for the peripheral design of controller, and validates the fault-tolerant performance of system under various fault conditions with modular joint test platform.The system use FPGA as the central controller and achieve fault-tolerant strategy to hardware circuit with Verilog. It integrates motor control unit and related fault-tolerant strategy in an FPGA chip with NIOSΠsoft core and SOPC technology, using hardware instead of software method to reduce system fault probability, the system get a high reliability and integrity.The achievement of this project provides a high fault-tolerance and efficiency solution which has a certain extent of application value to the design of long-life and hard real-time controller, meeting the requirement of control ability and fault-tolerance in the special environment.