Design Of16Bit Mash ADC For Silicon Gyroscope

With the continuous development of science and technology, application ofhigh accuracy of the device is more and more popular, especially in the aerospaceand medical etc. The traditional converter has high requirement to the componentsprecision and analog circuit, to achieve the16bit accuracy, a certain degree of designdifficulty for the existing process. While Sigma-Delta analog-to-digital converteruses noise shaping, oversampling and digital filtering technology, effectivelyreducing the quantization noise in the output signal in the band. Otherwise, iteffectively improves the signal-to-noise ratio, reduces the production cost andsimplifies the design of analog circuit.This paper firstly introduces the principle of Sigma-Delta modulator, andanalyzes the principle of the MASH structure of Sigma-Delta modulation, makes adetailed analysis on the parameters affecting the performance of modulator, and aspecific effect on the parameters is also analyzed.This paper is the design of a16bit Sigma-Delta converter applied to silicongyroscope, the system simulation is achieved in MATLAB environment, and circuitdesign in cadence and hspice. Firstly, system modeling, theoretical analysis todetermine all the details of the design of modulator, the cascaded2-1structure andthe cascaded2-1-1structure design, determine more appropriate structure bycomparing the two parameters. In addition, a detailed analysis of the impact of theirrational factors of the modulator, including coefficient mismatch, OPA finite DCgain, thermal noise, clock jitter, MOS switch error, and these irrational factors intothe system model for system level simulation. The following results were obtainedthrough the simulation of ideal and irrational situation: ideally, when the input signalbandwidth is100kHz, the2-1structure using.While oversampling rate is128,2-1structure achieved a signal-to-noise ratio of110.3dB, effective number of bits to reach18.02;2-1-1structure using oversamplingrate of64, the signal-to-noise ratio is121.8dB, effective number of bits to reach19.93. Joining the irrational factors, enter the same signal,2-1structure, using asampling rate of128, the signal-to-noise ratio is104.7dB, effective number of bits toreach17.09;2-1-1structure using oversampling rate of64, achieved asignal-to-noise ratio of111.6dB, effective number of bits to18.82bits. The designcan meet the design requirements of16. By contrast, can be found, the overallperformance of the2-1-1structure has more advantages, the design of the2-1-1 structure.Due to the signal bandwidth is larger, and the sampling rate is high, so higherrequirements for the circuit. Based on the design requirements completely fulfilled,respectively design for each module circuit, including an integrator, operationalamplifier, a quantizer, bandgap reference source and noise cancellation logic circuit,the DC gain of the amplifier is about78dB and the phase margin is61.6°, unit gainbandwidth of102MHz, meeting the behavioral simulation requirements ofoperational amplifier that gain is greater than80dB, unit gain bandwidth of morethan100MHz requirements. In the load capacitance of3pF, slew rate of142V/μ s,meets the behavioral simulation required slew rate is greater than100V/μ srequirements. The comparator delay is32ns, meet the design requirements. Theanalog and digital blocks together, can correctly realize the function, and the wholecircuit system simulation, effective number of bits to17.5bits, meet the designrequirements of the16, and for the layout design have a certain degree of.