Research&Design Of High-Speed Stochastic Flash ADC

The Flash ADC is widely used in wireless communication. However, withdevice size scaling, the offset of comparators in Flash ADC increases a lot, whichmakes it difficult to decrease the power and area of circuit. Based on Flash ADC,this work realizes a novel architecture, which is called stochastic Flash ADC. TheADC removes resistor series of Flash ADC, and utilizes the offsets in comparatorsas trip levels, treats the cumulative function of offsets as transition function.A pseudo differential dynamic comparator with high offset and little noise ischosen to comprise the comparator array. A Wallace tree composed of full adders isapplied to encode the digital output. On the study of stochastic Flash ADC’stransition character, a digital background calibration algorithm is proposed. Bycombining inverse function and piecewise approximation, the algorithm broadensthe ADC’s input range to maximum,-3σ~+3σ, thus promotes the transition functionto ideality. The circuit is simulated with TSMC65nm1.2V CMOS process, relyingon Spetre tools. The consequence of simulation shows the standard deviation ofcomparator’s offsets is40.1mv. The maximum of SNDR is42.48dB, and the meanof SNDR is41.78dB. The maximum of SFDR is47.86dB, and the mean is47dB.Besides the work above, a research on synthesizable all digital stochastic FlashADC is taken, and a way to broaden input range is proposed.