A780-MHz CMOS Ultra Low Power Receiver Design For Wireless Nodes In Internet Of Things

In recent decades, with the further improvement of the wireless communication‘requirement and the new technologies emerging, the probability that internet of things(IOT) wireless technology is widely used is more and more growing. And the lowpower technology of wireless nodes is one of the key technologies in IOT. Therefore,the paper is to study a low power wireless RF receiver, with researching the low powertechnologies in IOT wireless nodes.Firstly, the paper analysis some common wireless radio frequency (RF) receiver forthe IOT wireless nodes, include introducing the main performance of wireless RFreceiver such as system sensitivity, noise, carrier frequency, data rate, modulation modeand the power consumption of the system, and describing the advantages anddisadvantages of the different architectures of the receiver such as superheterodyne,zero intermediate frequency, low intermediate frequency and the envelope detector.Moreover, low power wireless receiver architecture and the corresponding performancefor wireless nodes is proposed at the basis of above analysis about the wireless RFreceiver‘s performance and architectures. Finally, the paper focus on discussing thelow-power envelope detector architecture applied in wireless nodes of IOT.The key blocks of low consumption receiver configured envelop detector includelow noise amplifier (LNA), RF programmable gain amplifier (RFPGA), envelopdetector (ED), limiter (LT) and analog to digital convert (ADC), the paper discusses indetail the performance specification, low consumption configure and circuit simulationof every block, especially LNA, RFPGA and ED. For LNA, two kinds of structures ofLNA that includes common-source based on the source inductor feedback andcommon-gate are analysis comparatively from the low consumption when MOS workedin sub-threshold region, as a result of adopting the low consumption common-gatestructure to circuit design. In order to improve the sensitivity of the system, RFprogrammable gain amplifier (RFPGA) adopts the four stages to amplify sign. Envelopedetector using common-source structure rather than the traditional source followingstructure can detect envelope and obtain enough gain. Finally, the paper discusses the whole circuit simulation and layout design of the key blocks of the ultra low powerwireless receiver operating at the780MHz, and the circuit and layout is optimized tomeet the requirements. Furthermore, the detailed measured proposal is presented toverify the function of the chip, and comparing to the measured result and simulation.Low consumption wireless receiver operating at the780MHz for wireless nodes inIOT is implemented in UMC65nm CMOS process, which adopts the simple structureand low power block envelop detector configure. The paper presents the circuit design,layout design and measure, and the measured result is similar as the simulation. Thereceiver chip size is1mm2, operating at the780MHz and bandwidth of20MHz, and thesensitivity of the receiver at a BER of0.001is-65dBm with4.2mW power consumptionat1.2V.