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The Research Of Countermeasure Against Power Analysis Attack In Block Cipher Applications

Posted on:2013-08-04Degree:MasterType:Thesis
Country:ChinaCandidate:Z YuanFull Text:PDF
GTID:2248330395985541Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
More and more attention has been putting on information security with thetechnological innovation of computer, communication and network. In order to securethe information transformation, modern cryptography such as block cipher providesan efficient and secure approach in embedded systems. Rijndael algorithm wasproposed by the National Institutes of Standards and Technology (NIST) to beAdvanced Encryption Standard (AES) in2001. From then on, AES became popularlyused in embedded systems, such as smart cards, mobile phone, Personal DigitalAssistant (PDA), Radio-Frequency Identification (RFID) and automotive electronics.In this research work, we firstly introduced Galois Field and AES. Then, wedescribed “Side Channel Attacks”, especially Power Analysis Attack which pose aserious threat to AES. Then, we introduced the defense technology such as hiding,shuffling, masking and secret sharing, and we drew the conclusion that the existingmethods have the drawbacks of larger area, lower speed, smaller throughput, andsome of them can not resist against High-Order Differential Power AnalysisAttack(HO-DPA) and glitch attack. Therefore, we proposed two new protectionmethods in this research work:The first method was a masking based countermeasure for AES over GF(24). Inthis method, we transformed the masked S-box from GF(28) to GF(24). The sixLook-Up Tables (LUT) were precomputed before encryption. Detailed designs of thenew S-box and AES were described, and we also proved the correctness for theproposed method.The second method was a secret sharing based countermeasure for AES. In thismethod, secret dividing functions were designed to divide the intermediate values intotwo shares. A random value was also introduced to enhance the security of the scheme.We described the designs of new S-box and AES and proved the correctness.In the end, we ported the above two designs to FPGA and ASIC platforms. Theexperimental results showed that the proposed methods achieved better performance,that is to say, less area, faster speed, larger throughput and with the ability to resistagainst HO-DPA and glitch attack compared with the existing methods.
Keywords/Search Tags:Block cipher, AES, Power Analysis Attack, Masking, Secret sharing, FPGA, ASIC
PDF Full Text Request
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