The Research And Implementation Of Key Modules Of FC-AE-1553Protocol Chip Based On PON Topology

With the continuous development of avionics systems, especially the requirementof large-capacity data transmission and real-time, traditional MIL-STD-1553bus hasbeen unable to fully meet the needs. Fibre Channel for its advantages ofhigh-bandwidth, low-latency, anti-jamming, easy to expand, etc… becomes prioritychoice of the next generation of aviation bus. FC-AE-1553protocol is designed tomake MIL-STD-1553protocol mapped to the agreement of the fiber-optic network. Itcan not only compatible with MIL-STD-1553bus, but also has the advantages of FibreChannel. So, it has broad application prospects in the future. The purpose of this articleis to realize the FC-AE-1553chip based on the PON topology. The main content of thearticle are as follows:This article first summarizes the research status of the FC-AE-1553protocol andthe PON topology and makes a brief analysis of the advantages of PON topologyapplied to FC-AE-1553protocol and the design characteristics. Then make an overallplane and design of the FC-AE-1553protocol chip based on PON topology. A shortintroduction of the overall function of the chip, the chip external interface, clockdomains, functional modules divided is made. Double buffer design of the storagecommands and other related information is convenient for the host computer and chipworking at the same time without conflict. According to the characteristics of the NCand TC, sharing storage and circular storage solutions are adopted.Secondly, a detailed description of the design is made to the key modules of thechip including the NC and NT task start and load modules, memory interface, receivermodule, transmitter module, transmission mode selection module, specific transferstate machine modules, bridge module. A simulation waveform data transfer mode ischosen to illustrate the working process of the module and the correctness of the design.The novelty of this design including a variety of functions and flexibility of task startand load module, the convergence of difference between the internal and externalmemory and memory interface designed to enhance the independence, the designreceive inter-clock domain processing combined with the characteristics of the protocol, etc.Finally, the functional correctness of the chip is verified on the FPGA verificationplatform with appropriate software by using Ethernet RGMII interface to simulate PCchip task configuration and chipscope means. After chip tapeout, the test process of thechip is introduced briefly. The chip tapeout is successful.In view of the great advantages of PON topology applied to FC-AE-1553protocoland some of the unique considerations of the chip design, it has great reference valuefor the follow up research and application based on the PON topology FC-AE-1553protocol.