Compression In Sar Real-time Imaging System And Matrix Transpose Study

The data volume and the high real-time are the two vital problems of Synthetic Aperture Radar (SAR) real-time imaging system. The data volume and computation task of SAR is huge, so it is necessary to be high-speed computation in SAR real-time processing. The computation task of SAR is concentrate on FFT, and usual hardware realization of FFT is using high speed DSP, but its disadvantage is small points. The data storage problem of the system is in the transpose of matrix (4K×8K). The main contents of this thesis can be concluded as following: 1. According to the task of the project, based on discussion of SAR key system parameter and thought of the block floating algorithm, introduce the design and realization of the block floating FFT algorithm based on the FPGA chip in the SAR processing system. And analyze the final hardware testing result. 2. For the problem of huge data storage, use SDRAM to store the data, and use FPGA to control SDRAM to complete the transpose. Because the control of SDRAM is very complex, this paper introduces the basic control of SDRAM and the design of how to control SDRAM to complete the transpose using FPGA in detail. Through the research of two important problems in SAR real-time processing, succeed in realizing of the block floating FFT based on FPGA, and complete the transpose using FPGA and SDRAM. It is very important for the whole system realizing. The design of the block floating FFT is valuable in military and civil application, and the complete of transpose is valuable for the later SAR real-time processing research.